參數(shù)資料
型號(hào)： AD9854ASQ
廠商： ANALOG DEVICES INC
元件分類(lèi)： XO, clock
英文描述： CMOS 300 MHz Quadrature Complete-DDS
中文描述： PLL FREQUENCY SYNTHESIZER, 30 MHz, PQFP80
封裝： MS-026-BEC, LQFP-80
文件頁(yè)數(shù)： 5/44頁(yè)
文件大?。?/td> 433K
代理商： AD9854ASQ
AD9854
–5–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin
No.
1–8
9, 10, 23,
24, 25, 73,
74, 79, 80
11, 12, 26,
27, 28, 72,
75, 76, 77,
78
13, 35, 57,
58, 63
14–19
Pin Name
D7–D0
DVDD
Function
Eight-Bit Bidirectional Parallel Programming Data Inputs. Used only in parallel programming mode.
Connections for the Digital Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
and DGND.
DGND
Connections for Digital Circuitry Ground Return. Same potential as AGND.
NC
No Internal Connection.
A5–A0
Six-Bit Parallel Address Inputs for Program Registers. Used only in parallel programming mode. A0, A1,
and A2 have a second function when the serial programming mode is selected. See immediately below.
Allows a RESET of the serial communications bus that is unresponsive due to improper program-
ming protocol. Resetting the serial bus in this manner does not affect previous programming nor
does it invoke the “default” programming values seen in the Table V. Active HIGH.
Unidirectional Serial Data Output for Use in 3-Wire Serial Communication Mode.
Bidirectional Serial Data Input/Output for Use in 2-Wire Serial Communication Mode.
Bidirectional Frequency Update Signal. Direction is selected in control register. If selected as an input,
a rising edge will transfer the contents of the programming registers to the internal works of the IC for
processing. If I/O UD is selected as an output, an output pulse (low to high) of eight system clock cycle
duration indicates that an internal frequency update has occurred.
Write Parallel Data to Programming Registers. Shared function with SCLK. Serial clock signal
associated with the serial programming bus. Data is registered on the rising edge. This pin is shared with
WRB when the parallel mode is selected.
Read Parallel Data from Programming Registers. Shared function with CSB. Chip-select signal
associated with the serial programming bus. Active LOW. This pin is shared with RDB when
the parallel mode is selected.
Multifunction Pin According to the Mode of Operation Selected in the Programming Control Register.
If in the FSK mode logic low selects F1, logic high selects F2. If in the BPSK mode, logic low selects
Phase 1, logic high selects Phase 2. If in the Chirp mode, logic high engages the HOLD function
causing the frequency accumulator to halt at its current location. To resume or commence Chirp,
logic low is asserted.
Must First Be Selected in the Programming Control Register to Function. A logic high will cause the
I and Q DAC outputs to ramp-up from zero-scale to full-scale amplitude at a preprogrammed rate.
Logic low causes the full-scale output to ramp-down to zero-scale at the preprogrammed rate.
Connections for the Analog Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
and DGND
(17)
A2/IO RESET
(18)
(19)
20
A1/SDO
A0/SDIO
I/O UD
21
WRB/SCLK
22
RDB/CSB
29
FSK/BPSK/
HOLD
30
SHAPED
KEYING
31, 32, 37,
38, 44, 50,
54, 60, 65
33, 34, 39,
40, 41, 45,
46, 47, 53,
59, 62, 66,
67
36
AVDD
AGND
Connections for Analog Circuitry Ground Return. Same potential as DGND.
VOUT
Internal High-Speed Comparator’s Noninverted Output Pin. Designed to drive 10 dBm to 50
load
as well as standard CMOS logic levels.
Voltage Input Positive. The internal high-speed comparator’s noninverting input.
Voltage Input Negative. The internal high-speed comparator’s inverting input.
Unipolar Current Output of the I or Cosine DAC.
Complementary Unipolar Current Output of the I or Cosine DAC.
Complementary Unipolar Current Output of the Q or Sine or DAC.
Unipolar Current Output of the Q or Sine DAC. This DAC can be programmed to accept
external 12-bit data in lieu of internal sine data. This allows the AD9854 to emulate the AD9852
control DAC function.
42
43
48
49
51
52
VINP
VINN
IOUT1
IOUT1B
IOUT2B
IOUT2
相關(guān)PDF資料
PDF描述
AD9854AST CMOS 300 MHz Quadrature Complete-DDS
AD9856AST CMOS 200 MHz Quadrature Digital Upconverter
AD9856 CMOS 180 MHz Quadrature Digital Upconverter(時(shí)鐘頻率為180MHz,CMOS的積分上變頻器)
AD9857 CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter
AD9857AST CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9854ASQZ 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP 制造商:Analog Devices 功能描述:Communication IC
AD9854AST 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ QUADRATURE DDS SYNTHESIZER - Tape and Reel 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS))
AD9854ASTZ 功能描述:IC DDS QUADRATURE CMOS 80-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9854ASVZ 制造商:Analog Devices 功能描述:CMOS 300 MSPS QUADRATURE COMPLETE DDS 制造商:Analog Devices 功能描述:CMOS 300 MSPS QUADRATURE COMPLETE DDS - Trays 制造商:Analog Devices 功能描述:SYNTHESIZER 制造商:Analog Devices 功能描述:Complete DDS Quadrature 300MSPS TQFP80
AD9854PCB 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:CMOS 300 MSPS Quadrature Complete DDS
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*