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參數(shù)資料
| 型號(hào)： | AD9849AKSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/32頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROC 12BIT 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號(hào)處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
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REV. A
AD9848/AD9849
–23–
Recommended Power-Up Sequence
When the AD9848 and AD9849 are powered up, the following
sequence is recommended (refer to Figure 14 for each step).
1. Turn on power supplies for AD9848/AD9849.
2. Apply the master clock input CLI, VD, and HD.
3. The Precision Timing core must be reset by writing a “0” to the
TGCORE_RSTB Register (Address x026) followed by writing
a “l(fā)” to the TGCORE_RSTB Register. This will start the inter-
nal timing core operation. Next, initialize the internal circuitry
by first writing “110101” or “53” decimal to the INITIAL1
Register (Address x020). Finally, write “000100” or “4” deci-
mal to the INITIAL2 Register (Address x00F).
4. Write a “1” to the PREVENTUPDATE Register (Address x019).
This will prevent the updating of the serial register data.
5. Write to desired registers to configure high speed timing and
horizontal timing.
6. Write a “1” to the OUT_CONT Register (Address x016). This
will allow the outputs to become active after the next VD/HD
rising edge.
7. Write a “0” to the PREVENTUPDATE Register (Address
x019). This will allow the serial information to be updated
at next VD/HD falling edge.
8. The next VD/HD falling edge allows register updates to occur,
including OUT_CONT, which enables all clock outputs.
ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9848/AD9849 signal processing chain is shown in
Figure 15. Each processing step is essential in achieving a high
quality image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc restore
circuit is used with an external 0.1
F series coupling capacitor.
This restores the dc level of the CCD signal to approximately 1.5 V
to be compatible with the 3 V analog supply signal of the
AD9848/AD9849.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low frequency noise. The timing
shown in Figure 6 illustrates how the two internally generated CDS
clocks, SHP and SHD, are used to sample the reference level
and data level of the CCD signal, respectively. The placement
of the SHP and SHD sampling edges is determined by the setting
of the SHPPOSLOC and SHDPOSLOC Registers located at
Address 0xF0 and 0xF1, respectively. Placement of these two clock
signals is critical to achieve the best performance from the CCD.
Input Clamp
A line-rate input clamping circuit removes the CCD’s optical black
offset. This offset exists in the CCD’s shielded black reference
pixels. The AD9848/AD9849 removes this offset in the input
stage to minimize the effect of a gain change on the system black
level, usually called the “gain step.” Another advantage of remov-
ing this offset at the input stage is to maximize system headroom.
Some area CCDs have large black level offset voltages that can
significantly reduce the available headroom in the internal circuitry
when higher VGA gain settings are used, if not corrected after
the input stage.
Horizontal timing examples are shown on the last page of the
Applications Information section. It is recommended that the
CLPDM pulse be used during valid CCD dark pixels. CLPDM
may be used during the optical black pixels, either together with
CLPOB or separately. The CLPDM pulse should be a minimum
of four pixels wide.
POWER-UP PROCEDURE
VDD
(INPUT)
SERIAL
WRITES
VD
(OUTPUT)
1 H
ODD FIELD
EVEN FIELD
...
DIGITAL
OUTPUTS
CLOCKS ACTIVE WHEN OUT_CONT REGISTER IS
UPDATED AT VD/HD EDGE
H1/H3, RG
H2/H4
tPWR
CLI
(INPUT)
HD
(OUTPUT)
1V
...
Figure 14. Recommended Power-Up Sequence
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| AD9849AKSTZRL | 功能描述:IC CCD SIGNAL PROC 12BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9849KST | 制造商:Rochester Electronics LLC 功能描述:12 BIT 25 MSPS 5V AFE & T - Tape and Reel 制造商:Analog Devices 功能描述: |
| AD9849KSTRL | 制造商:Analog Devices 功能描述:12 BIT 25 MSPS 5V AFE & T - Tape and Reel |
| AD9850 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS, 125 MHz Complete DDS Synthesizer |
| AD9850/CGPCB | 制造商:Analog Devices 功能描述:NCO/DDS, CMOS, 125MHZ COMPLETE DDS SYNTHESIZER - Bulk |
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