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| 型號(hào)： | AD9833BRMZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 21/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC WAVEFORM GEN PROG 10MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 25MHz |
| 調(diào)節(jié)字寬（位）： | 28 b |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
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AD9833
Data Sheet
Rev. E | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COMP
1
VDD
2
CAP/2.5V
3
DGND
4
MCLK
5
VOUT
10
AGND
9
FSYNC
8
SCLK
7
SDATA
6
AD9833
TOP VIEW
(Not to Scale)
02704-
005
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
COMP
DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
2
VDD
Positive Power Supply for the Analog and Digital Interface Sections. The on-board 2.5 V regulator is also supplied
from VDD. VDD can have a value from 2.3 V to 5.5 V. A 0.1 F and a 10 F decoupling capacitor should be connected
between VDD and AGND.
3
CAP/2.5V
The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from VDD using an on-board
regulator when VDD exceeds 2.7 V. The regulator requires a decoupling capacitor of 100 nF typical, which is
connected from CAP/2.5V to DGND. If VDD is less than or equal to 2.7 V, CAP/2.5V should be tied directly to VDD.
4
DGND
Digital Ground.
5
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
6
SDATA
Serial Data Input. The 16-bit serial data-word is applied to this input.
7
SCLK
Serial Clock Input. Data is clocked into the AD9833 on each falling edge of SCLK.
8
FSYNC
Active Low Control Input. FSYNC is the frame synchronization signal for the input data. When FSYNC is taken low,
the internal logic is informed that a new word is being loaded into the device.
9
AGND
Analog Ground.
10
VOUT
Voltage Output. The analog and digital output from the AD9833 is available at this pin. An external load resistor
is not required because the device has a 200 resistor on board.
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| AD9834BRU | 功能描述:IC DDS W/COMP 2.3V 50MHZ 20TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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