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參數資料
| 型號： | AD9833BRMZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 13/24頁 |
| 文件大小： | 0K |
| 描述： | IC WAVEFORM GEN PROG 10MSOP |
| 產品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標準包裝： | 1,000 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 25MHz |
| 調節(jié)字寬（位）： | 28 b |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
AD9833
Data Sheet
Rev. E | Page 20 of 24
INTERFACING TO MICROPROCESSORS
The AD9833 has a standard serial interface that allows the part to
interface directly with several microprocessors. The device uses
an external serial clock to write the data or control information
into the device. The serial clock can have a frequency of 40 MHz
maximum. The serial clock can be continuous, or it can idle high
or low between write operations. When data or control informa-
tion is written to the AD9833, FSYNC is taken low and is held
low until the 16 bits of data are written into the AD9833. The
FSYNC signal frames the 16 bits of information that are loaded
into the AD9833.
AD9833 TO 68HC11/68L11 INTERFACE
Figure 29 shows the serial interface between the AD9833 and
the 68HC11/68L11 microcontroller. The microcontroller is con-
figured as the master by setting the MSTR bit in the SPCR to 1.
This setting provides a serial clock on SCK; the MOSI output
drives the serial data line SDATA. Because the microcontroller
does not have a dedicated frame sync pin, the FSYNC signal is
derived from a port line (PC7). The setup conditions for correct
operation of the interface are as follows:
SCK idles high between write operations (CPOL = 0)
Data is valid on the SCK falling edge (CPHA = 1)
When data is being transmitted to the AD9833, the FSYNC line
is taken low (PC7). Serial data from the 68HC11/68L11 is trans-
mitted in 8-bit bytes with only eight falling clock edges occurring
in the transmit cycle. Data is transmitted MSB first. To load data
into the AD9833, PC7 is held low after the first eight bits are
transferred, and a second serial write operation is performed to
the AD9833. Only after the second eight bits are transferred
should FSYNC be taken high again.
AD9833
FSYNC
SDATA
SCLK
68HC11/68L11
PC7
MOSI
SCK
02704-
030
Figure 29. 68HC11/68L11 to AD9833 Interface
AD9833 TO 80C51/80L51 INTERFACE
Figure 30 shows the serial interface between the AD9833 and
the 80C51/80L51 microcontroller. The microcontroller is oper-
ated in Mode 0 so that TxD of the 80C51/80L51 drives SCLK of
the AD9833, and RxD drives the serial data line SDATA. The
FSYNC signal is derived from a bit programmable pin on the
port (P3.3 is shown in Figure 30).
When data is to be transmitted to the AD9833, P3.3 is taken low.
The 80C51/80L51 transmits data in 8-bit bytes, thus only eight
falling SCLK edges occur in each cycle. To load the remaining
eight bits to the AD9833, P3.3 is held low after the first eight
bits are transmitted, and a second write operation is initiated
to transmit the second byte of data. P3.3 is taken high following
the completion of the second write operation. SCLK should idle
high between the two write operations.
The 80C51/80L51 outputs the serial data in a format that has the
LSB first. The AD9833 accepts the MSB first (the four MSBs are
the control information, the next four bits are the address, and
the eight LSBs contain the data when writing to a destination
register). Therefore, the transmit routine of the 80C51/80L51
must take this into account and rearrange the bits so that the
MSB is output first.
AD9833
FSYNC
SDATA
SCLK
80C51/80L51
P3.3
RxD
TxD
02704-
031
Figure 30. 80C51/80L51 to AD9833 Interface
AD9833 TO DSP56002 INTERFACE
Figure 31 shows the interface between the AD9833 and the
DSP56002. The DSP56002 is configured for normal mode asyn-
chronous operation with a gated internal clock (SYN = 0, GCK = 1,
SCKD = 1). The frame sync pin is generated internally (SC2 = 1),
the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and the frame
sync signal frames the 16 bits (FSL = 0). The frame sync signal is
available on the SC2 pin, but it must be inverted before it is applied
to the AD9833. The interface to the DSP56000/DSP56001 is
similar to that of the DSP56002.
AD9833
FSYNC
SDATA
SCLK
DSP56002
SC2
STD
SCK
02704-
032
Figure 31. DSP56002 to AD9833 Interface
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