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參數(shù)資料
| 型號： | AD9826 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 16-Bit Imaging Signal Processor |
| 中文描述： | 完整的16位影像信號處理器 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 159K |
| 代理商： | AD9826 |
–3–
REV. A
AD9826
DIGITAL SPECIFICATIONS
Parameter
Symbol
Min
T yp
Max
Unit
LOGIC INPUT S
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
V
IH
V
IL
I
IH
I
IL
C
IN
2.0
V
V
μ
A
μ
A
pF
0.8
10
10
10
LOGIC OUT PUT S
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
V
OH
V
OL
I
OH
I
OL
4.5
V
V
μ
A
μ
A
0.1
50
50
LOGIC OUT PUT S (with DRVDD = 3 V)
High Level Output Voltage, (I
OH
= 50
μ
A)
Low Level Output Voltage (I
OL
= 50
μ
A)
V
OH
V
OL
2.95
V
V
0.05
Specifications subject to change without notice.
TIMNGSPECIFICATIONS
Parameter
Symbol
Min
T yp
Max
Unit
CLOCK PARAMET ERS
3-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulsewidth
CDSCLK 1 Pulsewidth
CDSCLK 2 Pulsewidth
CDSCLK 1 Falling to CDSCLK 2 Rising
ADCCLK Falling to CDSCLK 2 Rising
CDSCLK 2 Rising to ADCCLK Rising
CDSCLK 2 Falling to ADCCLK Falling
CDSCLK 2 Falling to CDSCLK 1 Rising
Aperture Delay for CDS Clocks
t
PRA
t
PRB
t
ADCLK
t
C1
t
C2
t
C1C2
t
ADC2
t
C2ADR
t
C2ADF
t
C2C1
t
AD
200
80
30
8
8
0
0
5
30
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
SERIAL INT ERFACE
Maximum SCLK Frequency
SLOAD to SCLK Set-Up T ime
SCLK to SLOAD Hold T ime
SDAT A to SCLK Rising Set-Up T ime
SCLK Rising to SDAT A Hold T ime
SCLK Falling to SDAT A Valid
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
RDV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
DAT A OUT PUT S
Output Delay
3-State to Data Valid
Output Enable High to 3-State
Latency (Pipeline Delay)
t
OD
t
DV
t
HZ
6
10
10
3 (Fixed)
ns
ns
ns
Cycles
NOT ES
It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.
Specifications subject to change without notice.
(T
MN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f
ADCCLK
= 15 MHz, f
CDSCLK1
= f
CDSCLK2
= 5 MHz,
C
L
= 10 pF, unless otherwse noted.)
(T
MN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, specs are for 16-bit performance.)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9826_12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 16-Bit Imaging Signal Processor |
| AD9826-EB | 制造商:Analog Devices 功能描述:- Bulk |
| AD9826KRS | 制造商:Analog Devices 功能描述:AFE Video 1ADC 16-Bit 5V 28-Pin SSOP Tube 制造商:Analog Devices 功能描述:IC 16-BIT SIGNAL PROCESSOR |
| AD9826KRSRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 16-Bit 5V 28-Pin SSOP T/R |
| AD9826KRSZ | 功能描述:IC IMAGE SGNL PROC 16BIT 28-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
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