參數(shù)資料
型號(hào)： AD9826
廠(chǎng)商： Analog Devices, Inc.
英文描述： Complete 16-Bit Imaging Signal Processor
中文描述： 完整的16位影像信號(hào)處理器
文件頁(yè)數(shù)： 2/20頁(yè)
文件大小： 159K
代理商： AD9826
–2–
REV. A
AD9826–SPECIFICATIONS
ANALOGSPECIFICATIONS
Parameter
Min
T yp
Max
Unit
MAX IMUM CONVERSION RAT E
3-Channel Mode with CDS
2-Channel Mode with CDS
1-Channel Mode with CDS
ACCURACY (ENT IRE SIGNAL PAT H)
ADC Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
No Missing Codes
ANALOG INPUT S
Input Signal Range (Programmable)
1
Allowable Reset T ransient
1
Input Limits
2
Input Capacitance
Input Bias Current
AMPLIFIERS
PGA Gain
PGA Gain Resolution
2
PGA Gain Monotonicity
Programmable Offset
Programmable Offset Resolution
Programmable Offset Monotonicity
NOISE AND CROSST ALK
T otal Output Noise @ PGA Minimum
T otal Output Noise @ PGA Maximum
Channel-to-Channel Crosstalk
@ 15 MSPS
@ 6 MSPS
POWER SUPPLY REJECT ION
AVDD = 5 V
0.25 V
DIFFERENT IAL VREF
(at 25
°
C)
CAPT –CAPB
T EMPERAT URE RANGE
Operating
Storage
POWER SUPPLIES
AVDD
DRVDD
OPERAT ING CURRENT
AVDD
DRVDD
Power-Down Mode
POWER DISSIPAT ION
3-Channel Mode
1-Channel Mode
30
30
18
MSPS
MSPS
MSPS
16
±
16
±
0.5
Bits
LSB
LSB
Guaranteed
2.0/4.0
1.0
V p-p
V
V
pF
nA
AVSS – 0.3
AVDD + 0.3
10
10
1
6
V/V
Steps
64
Guaranteed
–300
+300
mV
Steps
512
Guaranteed
3.0
9.0
LSB rms
LSB rms
70
90
dB
dB
0.1
% FSR
2.0
V
–40
–65
+85
+150
°
C
°
C
4.75
3.0
5.0
5.0
5.25
5.25
V
V
75
5
200
mA
mA
μ
A
400
300
mW
mW
NOT ES
Linear Input Signal Range is from 0 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9826’s input clamp.
4V SET BY INPUT CLAMP
(3V OPTION ALSO AVAILABLE)
4V p-p MAX INPUT SIGNAL RANGE
GND
1V TYP
RESET TRANSIENT
2
T he PGA Gain is approximately “l(fā)inear in dB” and follows the equation:
G
ain=
6.0
1+ 5.0
63 – G
63
where
G
is the register value.
Specifications subject to change without notice.
(T
MN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f
ADCCLK
= 15 MHz, f
CDSCLK1
= f
CDSCLK2
= 5 MHz, PGA
Gain = 1, Input range = 4 V p-p, unless otherwse noted.)
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