參數(shù)資料
型號: AD9807JS
廠商: ANALOG DEVICES INC
元件分類: 微控制器/微處理器
英文描述: Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQFP64
封裝: PLASTIC, QFP-64
文件頁數(shù): 21/24頁
文件大小: 240K
代理商: AD9807JS
AD9807/AD9805
–21–
REV. 0
CIS Application
Unlike many other integrated circuit CCD signal processors, the
AD9807/AD9805 can easily be implemented in imaging systems
that do not use a CCD. By disabling the input clamp and the
CDS blocks, any dc coupled signal within the input limits of the
part can be digitized. Figure 23 shows a typical block diagram of
the AD9807 used with a color CIS module, in this case Dyna
Image Corporation’s DL 100*. T he three color output signals
are dc coupled into the AD9807. T he Dyna CIS module’s
output levels are around 70 mV to 500 mV dark to bright, well
within the input range of the AD9807. T he AD9807 is config-
ured for 3-channel SHA operation through the MPU registers.
T iming used with the Dyna DL100 is shown in Figure 24; the
CIS output levels are sampled on the falling edge of CDSCLK 1.
T he digital ASIC shown can be implemented in a variety of
ways: it could include the MPU interface and timing generator,
as well as memory for the output data and pixel gain and offset
correction vectors.
RED
GREEN
BLUE
CIS
CLOCKS
VINR
VING
VINB
STRTLN,
CDSCLK1,
ADCCLK
OFFSET<7:0>
GAIN<11:0>
TIMING
GENERATOR
DIGITAL
ASIC
MPU
INTERFACE
PIXEL
OFFSET
CORRECTION
PIXEL
GAIN
CORRECTION
DOUT<11:0>
MPU<7:0>
A2, A1, A0
OEB, WRB
RDB, CSB
CIS
12
7
8
12
8
3
OUTPUT
DATA
AD9807
Figure 23. CIS Application Diagram (Power, Ground, and
Decoupling Omitted)
CIS START PULSE
CIS CLOCK
CIS OUTPUT
STRTLN
ADCCLK
CDSCLK1
Figure 24. CIS Application Timing Signals
E VALUAT ION BOARDS
T he AD9807 and AD9805 evaluation boards are designed to
provide an easy interface to a standard PC, simplifying the task
of evaluating the performance of the AD9807/AD9805 with an
existing imaging system. T he system level block diagram shown
in Figure 25 illustrates the basic evaluation setup for the
AD9807 (the AD9805 is the same). T he user needs to supply
the analog input signals (such as outputs from a CCD), the
AD9807/AD9805’s clock signals, a power supply and a printer
cable to connect the evaluation board to the PC’s parallel port.
Software is included to allow the user to easily accomplish three
major tasks: first, configure the AD9807/AD9805 in one of several
operating modes (1 Channel, 3 Channel, CDS or SHA mode,
etc.), second, acquire output data from the part and third, down-
load pixel gain and offset correction data to the evaluation board
and enable pixel rate shading and offset correction.
Figures 26 and 27 show the signal routing and decoupling for
the AD9807 evaluation board.
T he evaluation boards are designated with the part numbers
AD9807-EB and AD9805-EB.
*All trademarks are properties of their respective holders.
VINR
VING
VINB
CLOCKS
GAIN
OFFSET
DOUT
MPU I/O
MPU CONTROL
AD9807
RED
GREEN
BLUE
STRTLN
CDSCLK1
CDSCLK2
ADCCLK
4
12
8
12
8
7
FIFO
BUFFERS,
LATCHES,
AND
CONTROL
LOGIC
8
PRINTER
CABLE
PC
PARALLEL
PORT
AD9807 EVALUATION BOARD
+5V VOLT
POWER
SUPPLY
ANALOG INPUTS
CLOCK INPUTS
Figure 25. Evaluation System Block Diagram
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