- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17065 > AD9787-DPG2-EBZ (Analog Devices Inc)BOARD EVALUATION FOR AD9787 PDF資料下載
參數(shù)資料
| 型號： | AD9787-DPG2-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9787 |
| 標準包裝： | 1 |
| 系列： | * |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 800M |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時間： | 22ms |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | * |
| 已用 IC / 零件： | AD9787 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當(dāng)前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
AD9785/AD9787/AD9788
Rev. A | Page 42 of 64
DEVICE SYNCHRONIZATION
System demands may impose two different requirements for
synchronization. Some systems require multiple DACs to be
synchronized to each other, for example, a system that supports
transmit diversity or beamforming, where multiple antennas are
used to transmit a correlated signal. In this case, the DAC outputs
need to be phase aligned with each other, but there may not be a
requirement for the DAC outputs to be aligned with a system-
level reference clock. In systems with a time division multiplexing
transmit chain, one or more DACs may be required to be
synchronized with a system-level reference clock.
Multiple devices are considered synchronized to each other
when the state of the clock generation state machines is
identical for all parts and the NCO phase accumulator is
identical for all parts. Devices are considered synchronized to a
system clock when there is a fixed and known relationship
between the clock generation state machine and the NCO phase
accumulator of the device to a particular clock edge of the
system clock. The AD9785/AD9787/AD9788 support two
modes of operation, pulse mode and PN code mode, for
synchronizing devices under these two conditions.
SYNCHRONIZATION LOGIC OVERVIEW
Figure 60 shows a block diagram of the on-chip synchronization
receive logic. There are two different modes of operation for the
multichip synchronization feature: pulse mode and pseudorandom
noise code (PN code) modulation/demodulation mode. The basic
function of these two modes is to initialize the internal clock
generation state machine and the NCO phase accumulator
upon the application of external signals to the device.
The receive logic responsible for initializing the clock gener-
ation state machine generates a single DACCLK cycle-wide
initialization pulse that sets the clock generation state machine
logic to a known state. In pulse mode, this pulse is generated at
every rising edge of the SYNC_I inputs. In PN code mode, the
pulse is generated every time the correct code sequence is
received on the SYNC_I inputs.
This initialization pulse loads the clock generation state machine
with the Clock State [3:0] value (Register 0x03, Bits [7:4]) as its
next state. If the initialization pulse from the synchronization
logic is generated properly, it is active for one DAC clock cycle,
every 32 (or multiple of 32) DAC clock cycles. Because the clock
generation state machine has 32 states operating at the DACCLK
rate, every initialization pulse received after the first pulse loads
the current state (the state to which the state machine is already
set), maintaining the proper clock operation of the device.
The Clock State [3:0] value is the state to which the clock
generation state machine resets upon initialization. By varying
this value, the timing of the internal clocks, with respect to
the SYNC_I signal, can be adjusted. Every increment of the
Clock State [3:0] value advances the internal clocks by one
DACCLK period.
The NCO phase accumulators can be initialized in pulse mode
or PN code mode. In pulse mode, a simultaneous strobe signal
must be sent to the TXENABLE pin of all devices that is
synchronous to the DATACLK signal. This signal resets the
phase accumulator of the NCOs across all devices, effectively
synchronizing the NCOs.
In PN code mode, the phase information of the master device is
sent to the slave devices by the SYNC_I signal. The slave devices
decode this phase information and automatically initialize their
NCO phase accumulators to match the master device.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ESA10DTKS | CONN EDGECARD 20POS DIP .125 SLD |
| SDR0604-331KL | INDUCTOR POWER 330UH 10% SMD |
| AD9788-DPG2-EBZ | BOARD EVALUATION FOR AD9788 |
| SLPX223M025E7P3 | CAP ALUM 22000UF 25V 20% SNAP |
| EMA10DTKS | CONN EDGECARD 20POS DIP .125 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9787-EBZ | 制造商:Analog Devices 功能描述:DUAL 16B, D-A CONVERTER - Bulk |
| AD9788 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 12-/14-/16-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO |
| AD9788BSVZ | 功能描述:IC DAC 16BIT 800MSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD9788BSVZRL | 功能描述:IC DAC 16BIT 800MSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD9788-DPG2-EBZ | 功能描述:BOARD EVALUATION FOR AD9788 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。