參數(shù)資料
型號(hào)： AD9786
廠商： Analog Devices, Inc.
英文描述： 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing
中文描述： 16位，200 MSPS/500 MSPS的TxDAC系列2】/ 4】/ 8】插值與信號(hào)處理
文件頁(yè)數(shù)： 31/60頁(yè)
文件大?。?/td> 1497K
代理商： AD9786
AD9786
Note that the data in Figure 44 to Figure 53 was taken with the
DATAADJ default of 0000. With DCLKPOL = 0, the latching
edge of DACCLK is just previous to the rising edge of
DATACLK; with DCLKPOL = 1, the latching edge of DACCLK
is just previous to the falling edge of DATACLK. Table 27
describes the values available for 8× interpolation which gives a
choice of 16 edges to sync data. With 4× interpolation, there will
be a choice of 8 edges, and the relevant values from Table 27 will
be 0000, 0010, 0100, 0110, 1000, 1010, 1100, and 1110. These
options will allow latching edge placement from +3 cycles to
–4 cycles. In 2× interpolation, 4 edges will be available, and the
relevant values from Table 27 will be 0000, 0100, 1000, and 1100.
The choices for DATAADJ are diminished to +1 cycle to
–2 cycles.
Rev. 0 | Page 31 of 60
Figure 54, Figure 55, and Figure 56 show the alignment for the
latching edge of DACCLK with 4× interpolation and different
settings for DATAADJ. In Figure 54, the AD9786 is in
DATACLK Master Mode. DATAADJ is set to 0000, with
DCLKPOL set to 0 so that the latching edge of DACCLK is
immediately before the rising edge of DATACLK. The data
transitions shown in Figure 54 are synchronous with the
DACCLK, so that DACCLK and input data are constant with
respect to each other. The only visible change when DATAADJ
is altered is that DATACLK moves, indicating the latching edge
has moved as well. Note that in DATACLK Master Mode, when
DATAADJ is altered, the latching edge with respect to
DATACLK remains the same.
0
RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK
DATA TRANSITION
DACCLK
LATCHING EDGE
Figure 54. DATAADJ = 0000
Figure 55 shows the same conditions, but with DATAADJ set to
1111. This moves DATACLK to the left in the plot, indicating
that it occurs one DACCLK cycle before it did in Figure 54. As
explained previously, the latching edge of DACCLK also moves
one cycle back in time.
0
RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK
DATA TRANSITION
DACCLK
LATCHING EDGE
Figure 55. DATAADJ = 1111
Figure 56 shows the same conditions, with DATAADJ set to
0001, thus moving DATACLK to the right in the plot. This
indicates that it occurs one DACCLK cycle after it did in
Figure 54. In this case, the latching edge of DACCLK moves
forward in time one cycle.
0
RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK
DATA TRANSITION
DACCLK
LATCHING EDGE
Figure 56. DATAADJ = 0001
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