參數(shù)資料
型號： AD9786
廠商： Analog Devices, Inc.
英文描述： 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing
中文描述： 16位，200 MSPS/500 MSPS的TxDAC系列2】/ 4】/ 8】插值與信號處理
文件頁數(shù)： 27/60頁
文件大?。?/td> 1497K
代理商： AD9786
AD9786
With the interpolation set to 2×, the DACCLK input runs at
twice the speed of the DATACLK. Data is latched into the
digital inputs of the AD9786 on every other rising edge of
DACCLK, as shown in Figure 47 and Figure 48. With
DCLKPOL = 0, as shown in Figure 47, the latching edge of
DACCLK is the rising edge that occurs just before the falling
edge of DATACLK. With DCLKPOL = 1, as in Figure 48, the
latching edge of DACCLK is the rising edge of DACCLK that
occurs just before the rising edge of DATACLK. The setup
and hold time values are identical to those in Figure 44 and
Figure 45.
Rev. 0 | Page 27 of 60
Note that there is a slight difference in the delay from the rising
edge of DACCLK to the falling edge of DATACLK, and the
delay from the rising edge of DACCLK to the rising edge of
DATACLK. As Figure 46 shows, the DATACLK duty cycle is
slightly less than 50%. This is true in all modes.
With the interpolation set to 4× or 8×, the DACCLK input runs
at 4× or 8× the speed of the DATACLK output. The data is
latched in on a rising edge of DACCLK, similar to the 2×
interpolation mode. However, the latching edge is every fourth
edge in 4× interpolation mode and every eighth edge in the 8×
interpolation mode. Similar to operation in the 2× interpolation
mode, with DCLKPOL = 0, the latching edge of DACCLK is the
rising edge that occurs just before the falling edge of
DATACLK. With DCLKPOL = 1, the latching edge of DACCLK
is the rising edge that occurs just before the rising edge of
DATACLK. The setup and hold time values are identical to
those in 1× and 2× interpolation.
0
Figure 46.
t
D
= 5ns TYP
t
S
= –0.5ns MIN
t
H
= 2.9ns MIN
DACCLK
IN
DATACLK
OUT
DATA
0
Figure 47. Data Timing, 2× Interpolation, DCLKPOL = 0
0
t
D
= 6ns TYP
t
H
= 2.9ns MIN
t
S
= –0.5ns MIN
DACCLK
IN
DATACLK
OUT
DATA
Figure 48. Data Timing, 2× Interpolation, DCLKPOL = 1
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參數(shù)描述
AD9786BSV 制造商:Analog Devices 功能描述:DAC 1-CH Interpolation Filter 16-bit 80-Pin TQFP EP 制造商:Analog Devices 功能描述:IC 16BIT DAC SMD 9786 TQFP80
AD9786BSVRL 制造商:Analog Devices 功能描述:DAC 1-CH Interpolation Filter 16-bit 80-Pin TQFP EP T/R
AD9786BSVZ 功能描述:IC DAC 16BIT INTERPOL/SP 80TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 標準包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND
AD9786BSVZRL 功能描述:IC DAC 16BIT INTERPOL/SP 80TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:*
AD9786-EB 制造商:Rochester Electronics LLC 功能描述:EVAL BOARD FOR AD9786 - Bulk
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