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參數(shù)資料
| 型號： | AD9786 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing |
| 中文描述： | 16位，200 MSPS/500 MSPS的TxDAC系列2】/ 4】/ 8】插值與信號處理 |
| 文件頁數(shù)： | 20/60頁 |
| 文件大小： | 1497K |
| 代理商： | AD9786 |
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AD9786
MSB/LSB TRANSFERS
The AD9786 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by register address DATADIR
(00h[6]). The default is MSB first. When this bit is set active
high, the AD9786 serial port is in LSB first format. That is, if the
AD9786 is in LSB first mode, the instruction byte must be
written from least significant bit to most significant bit.
Multibyte data transfers in MSB format can be completed by
writing an instruction byte that includes the register address of
the most significant byte. In MSB first mode, the serial port
internal byte address generator decrements for each byte
required of the multibyte communication cycle. Multibyte data
transfers in LSB first format can be completed by writing an
instruction byte that includes the register address of the least
significant byte. In LSB first mode, the serial port internal byte
address generator increments for each byte required of the
multibyte communication cycle.
Rev. 0 | Page 20 of 60
The AD9786 serial port controller address will increment from
1Fh to 00h for multibyte I/O operations if the MSB first mode is
active. The serial port controller address will decrement from
00h to 1Fh for multibyte I/O operations if the LSB first mode
is active.
NOTES ON SERIAL PORT OPERATION
The AD9786 serial port configuration bits reside in Bits 6 and 7
of register address 00h. It is important to note that the
configuration changes immediately upon writing to the last bit
of the register. For multibyte transfers, writing to this register
may occur during the middle of communication cycle. Care
must be taken to compensate for this new configuration for the
remaining bytes of the current communication cycle.
The same considerations apply to setting the software reset,
SWRST (00h[5]) bit. All other registers are set to their default
values, but the software reset does not affect the bits in Register
Address 00h and 04h.
It is recommended to use only single byte transfers when
changing serial port configurations or initiating a soft-
ware reset.
R/W N0
N1
A0 A1
A2
A3
A4
D7 D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
D7 D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
0
Figure 37. Serial Register Interface Timing MSB First
A0
A1
A2
A3 A4
N1
N0 R/W D0
0
D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
D0
0
D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
0
Figure 38. Serial Register Interface Timing LSB First
INSTRUCTION BIT 6
INSTRUCTION BIT 7
CSB
SCLK
SDIO
t
DS
t
DS
t
DH
t
PWH
t
PWL
t
SCLK
0
Figure 39. Timing Diagram for Register Write
DATA BIT n–1
DATA BIT n
CSB
SCLK
SDIO
SDO
0
t
DV
Figure 40. Timing Diagram for Register Read
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| AD9786BSVZ | 功能描述:IC DAC 16BIT INTERPOL/SP 80TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC+® 標準包裝:1 系列:- 設置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD9786BSVZRL | 功能描述:IC DAC 16BIT INTERPOL/SP 80TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC+® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD9786-EB | 制造商:Rochester Electronics LLC 功能描述:EVAL BOARD FOR AD9786 - Bulk |
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