參數(shù)資料
型號: AD9778BSVZ
廠商: Analog Devices Inc
文件頁數(shù): 4/56頁
文件大?。?/td> 0K
描述: IC DAC 14BIT DUAL 1GSPS 100TQFP
產(chǎn)品培訓模塊: DAC Architectures
標準包裝: 1
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 300mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
輸出數(shù)目和類型: 4 電流,單極;4 電流,雙極
采樣率(每秒): 1G
AD9776/AD9778/AD9779
Rev. A | Page 12 of 56
Pin
No.
Mnemonic
Description
41
P2D<12>
Port 2, Data Input D12.
42
P2D<11>
Port 2, Data Input D11.
43
DVDD18
1.8 V Digital Supply.
44
DGND
Digital Common.
45
P2D<10>
Port 2, Data Input D10.
46
P2D<9>
Port 2, Data Input D9.
47
P2D<8>
Port 2, Data Input D8.
48
P2D<7>
Port 2, Data Input D7.
49
P2D<6>
Port 2, Data Input D6.
50
P2D<5>
Port 2, Data Input D5.
51
P2D<4>
Port 2, Data Input D4.
52
P2D<3>
Port 2, Data Input D3.
53
DVDD18
1.8 V Digital Supply.
54
DGND
Digital Common.
55
P2D<2>
Port 2, Data Input D2.
56
P2D<1>
Port 2, Data Input D1.
57
P2D<0>
Port 2, Data Input D0 (LSB).
58
NC
No Connect.
59
NC
No Connect.
60
DVDD18
1.8 V Digital Supply.
61
DVDD33
3.3 V Digital Supply.
62
SYNC_O
Differential Synchronization Output.
63
SYNC_O+
Differential Synchronization Output.
64
DGND
Digital Common.
65
PLL_LOCK
PLL Lock Indicator.
66
SDO
SPI Port Data Output.
67
SDIO
SPI Port Data Input/Output.
68
SCLK
SPI Port Clock.
69
CSB
SPI Port Chip Select Bar.
70
RESET
Reset, Active High.
71
IRQ
Interrupt Request.
72
AGND
Analog Common.
73
IPTAT
Factory Test Pin. Output current is
proportional to absolute temperature,
approximately 10 μA at 25°C with
approximately 20 nA/°C slope. This
pin should remain floating.
Pin
No.
Mnemonic
Description
74
VREF
Voltage Reference Output.
75
I120
120 μA Reference Current.
76
AVDD33
3.3 V Analog Supply.
77
AGND
Analog Common.
78
AVDD33
3.3 V Analog Supply.
79
AGND
Analog Common.
80
AVDD33
3.3 V Analog Supply.
81
AGND
Analog Common.
82
AGND
Analog Common.
83
OUT2_P
Differential DAC Current Output,
Channel 2.
84
OUT2_N
Differential DAC Current Output,
Channel 2.
85
AGND
Analog Common.
86
AUX2_P
Auxiliary DAC Current Output,
Channel 2.
87
AUX2_N
Auxiliary DAC Current Output,
Channel 2.
88
AGND
Analog Common.
89
AUX1_N
Auxiliary DAC Current Output,
Channel 1.
90
AUX1_P
Auxiliary DAC Current Output,
Channel 1.
91
AGND
Analog Common.
92
OUT1_N
Differential DAC Current Output,
Channel 1.
93
OUT1_P
Differential DAC Current Output,
Channel 1.
94
AGND
Analog Common.
95
AGND
Analog Common.
96
AVDD33
3.3 V Analog Supply.
97
AGND
Analog Common.
98
AVDD33
3.3 V Analog Supply.
99
AGND
Analog Common.
100
AVDD33
3.3 V Analog Supply.
1 The combined differential clock input at the CLK+ and CLK– pins are referred
to as REFCLK.
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