參數(shù)資料
型號(hào)： AD9761-EB
廠商： Analog Devices, Inc.
英文描述： Dual 10-Bit TxDAC+⑩ with 2x Interpolation Filters
中文描述： 雙10位TxDAC系列⑩2倍內(nèi)插濾波器
文件頁(yè)數(shù)： 6/23頁(yè)
文件大小： 246K
代理商： AD9761-EB
AD9761
–6–
REV. A
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
1
2–9
10
11
DB9
DB8–DB1
DB0
CLOCK
Most Significant Data Bit (MSB).
Data Bits 1-8.
Least Significant Data Bit (LSB).
Clock Input. Both DACs’ outputs updated on positive edge of clock and digital filters read respective
input registers.
Write input. DAC input registers latched on positive edge of write.
Select Input. Select high routes input data to I DAC, select low routes data to Q DAC.
Digital Supply Voltage (+2.7 V to +5.5 V).
Digital Common.
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1
μ
F capacitor.
Q DAC Current Output. Full-scale current when all data bits are 1s.
Q DAC Complementary Current Output. Full-scale current when all data bits are 0s.
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal
reference.
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.2 V
reference output when internal reference activated. Requires 0.1
μ
F capacitor to ACOM when inter-
nal reference activated.
Full-Scale Current Output Adjust. Resistance to ACOM sets full-scale output current.
Bandwidth/Noise Reduction Node. Add 0.1
μ
F to AVDD for optimum performance.
Analog Supply Voltage (+2.7 V to +5.5 V).
Analog Common.
I DAC Complementary Current Output. Full-scale current when all data bits are 0s.
I DAC Current Output. Full-scale current when all data bits are 1s.
Internal Bias Node for Switch Driver Circuitry. Decouple to AGND with 0.1
μ
F capacitor.
Power-Down control input if asserted for four clock cycles or longer. Reset control input if asserted
for less than four clock cycles. Active high. Connect to DCOM if not used. Refer to RESET/SLEEP
section.
12
13
14
15
16
17
18
19
WRITE
SELECT
DVDD
DCOM
COMP3
QOUTA
QOUTB
REFLO
20
REFIO
21
22
23
24
25
26
27
28
FSADJ
COMP2
AVDD
ACOM
IOUTB
IOUTA
COMP1
RESET/SLEEP
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9761
(MSB) DB9
IOUTB
IOUTA
COMP1
RESET/SLEEP
DB8
DB7
DB6
COMP2
AVDD
ACOM
DB5
DB4
DB3
DB2
DB1
(LSB) DB0
REFLO
REFIO
FSADJ
CLOCK
WRITE
SELECT
DVDD
QOUTB
DCOM
COMP3
QOUTA
相關(guān)PDF資料
PDF描述
AD9761ARS Dual 10-Bit TxDAC+⑩ with 2x Interpolation Filters
AD9761 Dual 10-Bit TxDAC with 23 Interpolation Filters(內(nèi)插濾波器的雙10位D/A轉(zhuǎn)換器)
AD9762 Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table
AD9762-EB 12-Bit, 125 MSPS TxDAC D/A Converter
AD9762AR 12-Bit, 125 MSPS TxDAC D/A Converter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9761-EBZ 功能描述:BOARD EVAL FOR AD9761 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
AD9762 制造商:AD 制造商全稱:Analog Devices 功能描述:Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table
AD9762AR 功能描述:IC DAC 12BIT 125MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k
AD9762ARRL 功能描述:IC DAC 12BIT 100KSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:*
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