IOUTA IOUTB C" />
參數(shù)資料
型號: AD9751ASTZ
廠商: Analog Devices Inc
文件頁數(shù): 10/28頁
文件大?。?/td> 0K
描述: IC DAC 10BIT 300MSPS 48-LQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
系列: TxDAC+®
設(shè)置時間: 11ns
位數(shù): 10
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 165mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 300M
產(chǎn)品目錄頁面: 785 (CN2011-ZH PDF)
配用: AD9751-EB-ND - BOARD EVAL FOR AD9751
REV. C
AD9751
–18–
AD9751
IOUTA
IOUTB
COPT
200
VOUT = IOUTFS
RFB
200
Figure 24. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS, POWER
SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these applications, the
implementation and construction of the printed circuit board is
as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing, as well
as power supply bypassing and grounding, to ensure optimum
performance. Figures 34 to 41 illustrate the recommended
printed circuit board ground, power, and signal plane layouts
that are implemented on the AD9751 evaluation board.
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the Power Supply Rejection Ratio. For dc
variations of the power supply, the resulting performance of the
DAC directly corresponds to a gain error associated with the
DAC’s full-scale current, IOUTFS. AC noise on the dc supplies is
common in applications where the power distribution is gener-
ated by a switching power supply. Typically, switching power
supply noise occurs over the spectrum from tens of kHz to sev-
eral MHz. The PSRR versus frequency of the AD9751 AVDD
supply over this frequency range is shown in Figure 25.
FREQUENCY (MHz)
85
40
12
6
0
PSRR
(dB)
80
75
70
65
60
55
50
45
24
8
10
Figure 25. Power Supply Rejection Ratio
Note that the units in Figure 25 are given in units of (amps out/
volts in). Noise on the analog power supply has the effect of modu-
lating the internal switches, and therefore the output current.
The voltage noise on AVDD is thus added in a nonlinear man-
ner to the desired IOUT. Due to the relative different size of these
switches, PSRR is very code-dependent. This can produce a
mixing effect that can modulate low frequency power supply
noise to higher frequencies. Worst-case PSRR for either one of
the differential DAC outputs occurs when the full-scale current is
directed toward that output. As a result, the PSRR measure-
ment in Figure 25 represents a worst-case condition in which
the digital inputs remain static and the full-scale output current
of 20 mA is directed to the DAC output being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV rms of noise and, for the
sake of simplicity (i.e., ignore harmonics), all of this noise is
concentrated at 250 kHz. To calculate how much of this undes-
ired noise will appear as current noise superimposed on the
DAC’s full-scale current, IOUTFS, one must determine the PSRR
in dB using Figure 25 at 250 kHz. To calculate the PSRR for a
given RLOAD, such that the units of PSRR are converted from
A/V to V/V, adjust the curve in Figure 25 by the scaling factor
20
log (RLOAD). For instance, if RLOAD is 50
, the PSRR is
reduced by 34 dB, i.e., PSRR of the DAC at 250 kHz, which is
85 dB in Figure 25, becomes 51 dB VOUT/VIN.
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9751 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a sys-
tem. In general, AVDD, the analog supply, should be decoupled
to ACOM, the analog common, as close to the chip as physi-
cally possible. Similarly, DVDD, the digital supply, should be
decoupled to DCOM as close to the chip as physically possible.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply may be
generated using the circuit shown in Figure 26. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESR
type electrolytic and tantalum capacitors.
AVDD
ACOM
100 F
ELECT.
10 F–22 F
TANT.
0.1 F
CER.
TTL/CMOS
LOGIC
CIRCUITS
3.3V
POWER SUPPLY
FERRITE
BEADS
Figure 26. Differential LC Filter for a Single 3.3 V Application
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