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| 型號： | AD9751 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit,300 MSPS High Speed T×DAC+TM D/A Converter(300MSPS,超高速,單通道10位D/A轉(zhuǎn)換器) |
| 中文描述： | 10位，300 MSPS的高速厚×援商標(biāo)D / A轉(zhuǎn)換（300MSPS，超高速，單通道10位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 156K |
| 代理商： | AD9751 |
9 REV. PrA
DATA
TECHNCAL
OUT A
and I
OUT B
such as noise, distortion and dc offsets. Second, the
differential code dependent current and subsequent
voltage, V
DIFF
, is twice the value of the single-ended
voltage output (i.e., V
OUT A
or V
OUT B
), thus providing
twice the signal power to the load.
Note, that the gain drift temperature performance for a
single-ended (V
OUT A
and V
OUT B
) or differential output
(V
DIFF
) of the AD9751 can be enhanced by selecting
temperature tracking resistors for R
LOAD
and R
SET
due
to their ratiometric relationship as shown in Equation
8.
AD9751
tS
Figure 9. AD9751 Timing Requirements, Interleaving
Data with PLL Disabled
data y
tH
data x
DAT A IN
PORT 2
2
×
CLK
tLPW
tPD
data y
data x
IOUT A
OR
IOUT B
DAT A IN
PORT 1
DELAYED
1
×
CLK
tPD
tD
NON-INTERLEAVED DATA WITH PLL DISABLED
If the data at only one port is required, no interleaving
is done, and the AD9751 interface operates as a typical
double buffered latch. On the rising edge of the
1×
clock, input latch 1 or 2 is updated with the present
input data. On the next rising edge, the DAC latch is
updated and a propagation time later the DAC output
reflects this change. Figure 10 represents the AD9751
timing in this mode.
DAT A IN
PORT 1 or
PORT 2
tS
tH
×
1 CLOCK
tLPW
tPD
IOUT A
OR
IOUT B
DAT A OUT
PORT 1 or
PORT 2
X X
Figure 10. AD9751 Timing Requirements, Non-
Interleaved Data with PLL Disabled
DAC TRANSFER FUNCTION
T he AD9751 provides complementary current outputs,
IOUT A and IOUT B. IOUT A will provide a near full-
scale current output, I
OUT FS
, when all bits are high (i.e.,
DAC CODE = 1023) while IOUT B, the complemen-
tary output, provides no current. T he current output
appearing at IOUT A and IOUT B is a function of both
the input code and I
OUT FS
and can be expressed as:
I
OUT A
= (DAC CODE/1024)
×
I
OUT FS
I
OUT B
= (1023 – DAC CODE)/1024
×
I
OUT FS
(2)
(1)
where DAC CODE = 0 to 1023 (i.e., Decimal
Representation).
As mentioned previously, I
OUT FS
is a function of the
reference current I
REF
, which is nominally set by a
reference voltage, V
REFIO
and external resistor R
SET
. It
can be expressed as:
I
OUT FS
= 32
×
I
REF
where I
REF
= V
REFIO
/R
SET
T he two current outputs will typically drive a resistive
load directly or via a transformer. If dc coupling is
required, IOUT A and IOUT B should be directly
connected to matching resistive loads, R
LOAD
, that are
tied to analog common, ACOM. Note, R
LOAD
may
represent the equivalent load resistance seen by
IOUT A or IOUT B as would be the case in a doubly
terminated 50
or 75
cable. T he single-ended voltage
output appearing at the IOUT A and IOUT B nodes is
simply :
V
OUT A
= I
OUT A
×
R
LOAD
V
OUT B
= I
OUT B
×
R
LOAD
(3)
(4)
(5)
(6)
Note the full-scale value of V
OUT A
and V
OUT B
should not
exceed the specified output compliance range to
maintain specified distortion and linearity perfor-
mance.
V
DIFF
= (I
OUT A
– I
OUT B
)
×
R
LOAD
Substituting the values of I
OUT A
, I
OUT B
and I
REF
; V
DIFF
V
DIFF
= {(2 DAC CODE – 1023)/1024}
×
(32 R
LOAD
/R
SET
)
×
V
REFIO
T hese last two equations highlight some of the advan-
tages of operating the AD9751 differentially. First,
the differential operation will help cancel common-
(7)
(8)
ANALOG OUTPUTS
T he AD9751 produces two complementary current
outputs, I
OUT A
and I
OUT B
, which may be configured for
single-ended or differential operation. I
OUT A
and I
OUT B
can be converted into complementary single-ended
voltage outputs, V
OUT A
and V
OUT B
, via a load resistor,
R
LOAD
, as described in the DAC T RANSFER FUNC-
T ION section by Equations 5 through 8. T he differ-
ential voltage, V
DIFF
, existing between V
OUT A
and V
OUT B
can also be converted to a single-ended voltage via a
transformer or differential amplifier configuration. T he
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