參數(shù)資料
型號(hào)： AD9707BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 7/44頁
文件大?。?/td> 0K
描述： IC DAC TX 14BIT 175MSPS 32-LFCSP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
設(shè)置時(shí)間： 11ns
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 50mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 托盤
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 175M
產(chǎn)品目錄頁面： 785 (CN2011-ZH PDF)
Data Sheet
AD9704/AD9705/AD9706/AD9707
Rev. B | Page 15 of 44
AD9704
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
8
7
6
5
4
3
2
1
NC
DVDD
DB0 (LSB)
DB1
17
18
19
20
21
22
23
24
PIN/SPI/RESET
AVDD
OTCM
IOUTB
IOUTA
ACOM
REFIO
FS ADJ
16
15
14
13
12
11
10
9
M
O
DE
/S
DI
O
CM
O
DE
/S
CL
K
CL
KV
DD
CL
KCO
M
CL
K–
CL
K
+
DCO
M
NC
25
26
27
28
29
30
31
32
SL
EEP
/C
SB
DCO
M
DB7
(
M
S
B
)
DB6
DB5
DB4
DB3
DB2
05
92
6-
0
84
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE
THERMALLY CONNECTED TO A COPPER GROUND
PLANE FOR ENHANCED ELECTRICAL AND THERMAL
PERFORMANCE.
Figure 6. AD9704 Pin Configuration
Table 12. AD9704 Pin Function Descriptions
Pin No.
Mnemonic
Description
28 to 32, 1
DB6 to DB1
Data Bit 6 to Data Bit 1.
2
DB0 (LSB)
Least Significant Data Bit (LSB).
3
DVDD
Digital Supply Voltage (1.7 V to 3.6 V).
4 to 9
NC
No Connect.
10, 26
DCOM
Digital Common.
11
CLKVDD
Clock Supply Voltage (1.7 V to 3.6 V).
12
CLK+
Positive Differential Clock Input.
13
CLK
Negative Differential Clock Input.
14
CLKCOM
Clock Common.
15
CMODE/SCLK
In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver (drive CLK+
and float CLK). Connect to CLKVDD for differential receiver. In SPI mode, this pin is the serial data clock input.
16
MODE/SDIO
In pin mode, this pin selects the input data format. Connect to DCOM for straight binary, and DVDD for twos
complement. In SPI mode, this pin acts as SPI data input/output.
17
PIN/SPI/RESET
Selects SPI Mode or Pin Mode Operation. Active high for pin mode operation and active low for SPI mode
operation. Pulse high to reset SPI registers to default values.
18
AVDD
Analog Supply Voltage (1.7 V to 3.6 V).
19
OTCM
Adjustable Output Common Mode. Refer to the Theory of Operation section for details.
20
IOUTB
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
21
IOUTA
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
22
ACOM
Analog Common.
23
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference output
when internal reference is activated. Requires a 0.1 μF capacitor to ACOM when internal reference is activated.
24
FS ADJ
Full-Scale Current Output Adjust.
25
SLEEP/CSB
In pin mode, active high powers down chip. In SPI mode, this pin is the serial port chip select (active low).
27
DB7 (MSB)
Most Significant Data Bit (MSB).
EPAD
It is recommended that the exposed pad be thermally connected to a copper ground plane for enhanced
electrical and thermal performance.
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