參數(shù)資料
型號： AD9707BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 28/44頁
文件大?。?/td> 0K
描述： IC DAC TX 14BIT 175MSPS 32-LFCSP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
設(shè)置時間： 11ns
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 50mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 托盤
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 175M
產(chǎn)品目錄頁面： 785 (CN2011-ZH PDF)
AD9704/AD9705/AD9706/AD9707
Data Sheet
Rev. B | Page 34 of 44
Table 20. MEMRDWR—Register 0x0F
Mnemonic
Bit No.
Direction (I/O)
Default
Description
CALSTAT
7
O
0
1 = calibration cycle complete
CALEN
6
I
0
1 = initiates device self-calibration
SMEMWR
3
I
0
1 = writes to static memory (calibration coefficients)
SMEMRD
2
I
0
1 = reads from static memory (calibration coefficients)
UNCAL
0
I
0
1 = resets calibration coefficients to default (uncalibrated)
Table 21. MEMADDR—Register 0x10
Mnemonic
Bit No.
Direction (I/O)
Default
Description
MEMADDR[5:0]
[5:0]
I/O
000000
Address of static memory to be accessed
Table 22. MEMDATA—Register 0x11
Mnemonic
Bit No.
Direction (I/O)
Default
Description
MEMDATA[5:0]
[5:0]
I/O
111111
Data for static memory access
REFERENCE OPERATION
An external reference can be used in applications requiring
tighter gain tolerances or lower temperature drift. Also, a variable
external voltage reference can be used to implement a method
for gain control of the DAC output. The external reference is
applied to the REFIO pin. Note that the 0.1 μF compensation
capacitor is not required. The internal reference can be directly
overdriven by the external reference, or the internal reference
can be powered down. The input impedance of REFIO is 10 kΩ
when powered up and 1 MΩ when powered down.
The AD9704/AD9705/AD9706/AD9707 contain an internal 1.0 V
band gap reference. The internal reference can be disabled by
writing a Logic 1 to Register 0x00, Bit 0 (EXREF) in the SPI.
To use the internal reference, decouple the REFIO pin to ACOM
with a 0.1 μF capacitor, enable the internal reference by writing
a Logic 0 to Register 0x00, Bit 0 in the SPI. (Note that this is the
default configuration.) The internal reference voltage is present
at REFIO. If the voltage at REFIO is to be used anywhere else in
the circuit, an external buffer amplifier with an input bias current of
less than 100 nA must be used to avoid loading the reference. An
example of the use of the internal reference is shown in Figure 78.
REFERENCE CONTROL AMPLIFIER
The AD9704/AD9705/AD9706/AD9707 contain a control
amplifier that regulates the full-scale output current, IOUTFS. The
control amplifier is configured as a V-I converter, as shown in
Figure 78. The output current, IREF, is determined by the ratio of
the VREFIO and an external resistor, RSET, as stated in Equation 4.
IREF is mirrored to the segmented current sources with the
proper scale factor to set IOUTFS, as stated in Equation 3.
CURRENT
SCALING
x32
AD9704/AD9705/
AD9706/AD9707
DAC
IOUTFS
RSET
0.1F
REFIO
IREF
AVSS
FS ADJ
VBG
1.0V
+
–
0
59
26-
09
4
Figure 78. Internal Reference Configuration
REFIO serves as either an input or an output, depending on
whether the internal or an external reference is used. Table 23
summarizes the reference operation.
The control amplifier allows a 5:1 adjustment span of IOUTFS from
1 mA to 5 mA by setting IREF between 31.25 μA and 156.25 μA
(RSET between 6.4 kΩ and 32 kΩ). The wide adjustment span of
IOUTFS provides several benefits. The first relates directly to the
power dissipation of the AD9704/AD9705/AD9706/ AD9707,
which is proportional to IOUTFS (see the Power Dissipation section).
The second benefit relates to the ability to adjust the output over a
14 dB range, which is useful for controlling the transmitted power.
Table 23. Reference Operation
Reference
Mode
REFIO Pin
Register Setting
Internal
Connect 0.1 μF capacitor
Register 0x00, Bit 0 = 0
(default)
External
Apply external reference
Register 0x00, Bit 0 = 1
(for power saving)
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