參數資料
型號: AD9648BCPZRL7-125
廠商: Analog Devices Inc
文件頁數: 43/44頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 125MSPS 64LFCSP
標準包裝: 750
位數: 14
采樣率(每秒): 125M
數據接口: LVDS,并聯(lián),串行,SPI
轉換器數目: 2
電壓電源: 模擬和數字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應商設備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數目和類型: 4 個單端,2 個差分
AD9648
Rev. 0 | Page 8 of 44
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless
otherwise noted.
Table 4.
AD9648-105
AD9648-125
Parameter
Temp
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK INPUT PARAMETERS
Input Clock Rate
Full
1000
MHz
Conversion Rate1
DCS Enabled
Full
20
105
20
125
MSPS
DCS Disabled
Full
10
105
10
125
MSPS
CLK Period—Divide-by-1 Mode (t
CLK)
Full
9.52
8
ns
CLK Pulse Width High (t
CH)
Full
4.76
4
ns
Aperture Delay (t
A)
Full
1.0
ns
Aperture Uncertainty (Jitter, t
J)
Full
0.07
ps rms
DATA OUTPUT PARAMETERS
CMOS Mode (DRVDD = 1.8 V)
Data Propagation Delay (t
PD)
Full
1.8
2.9
4.4
1.8
2.9
4.4
ns
DCO Propagation Delay (t
DCO)
Full
2.0
3.1
4.4
2.0
3.1
4.4
ns
DCO to Data Skew (t
SKEW)
Full
1.2
0.1
+1.0
1.2
0.1
+1.0
ns
LVDS Mode (DRVDD = 1.8 V)
Data Propagation Delay (t
PD)
Full
2.4
ns
DCO Propagation Delay (t
DCO)
Full
2.4
ns
DCO to Data Skew (t
SKEW)
Full
0.20
+0.03
+0.25
0.20
+0.03
+0.25
ns
CMOS Mode Pipeline Delay (Latency)
Full
16
Cycles
LVDS Mode Pipeline Delay (Latency) Channel A/Channel B
Full
16/16.5
Cycles
Wake-Up Time (Power Down)3
Full
350
s
Wake-Up Time (Standby)
Full
250
ns
Out-of-Range Recovery Time
Full
2
Cycles
1 Conversion rate is the clock rate after the divider.
2 Additional DCO delay can be added by writing to Bits[2:0] in SPI Register 0x17 (see Table 18).
3 Wake-up time is defined as the time required to return to normal operation from power-down mode.
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