tPD tSKEW
參數(shù)資料
型號: AD9648BCPZRL7-125
廠商: Analog Devices Inc
文件頁數(shù): 2/44頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 125MSPS 64LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 14
采樣率(每秒): 125M
數(shù)據(jù)接口: LVDS,并聯(lián),串行,SPI
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,2 個差分
AD9648
Rev. 0 | Page 10 of 44
tPD
tSKEW
tCH
tDCO
tCLK
CH A
N – 16
CH B
N – 15
CH A
N – 14
CH B
N – 13
CH A
N – 12
CH B
N – 11
CH A
N – 10
CH B
N – 9
CH A
N – 8
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
VIN
CLK+
CLK–
CH A DATA
DCOA/DCOB
tA
CH B DATA
CH B
N – 16
CH A
N – 15
CH B
N – 14
CH A
N – 13
CH B
N – 12
CH A
N – 11
CH B
N – 10
CH A
N – 9
CH B
N – 8
09975-
003
Figure 3. CMOS Interleaved Output Mode Data Output Timing
tPD
tSKEW
tCH
tDCO
tCLK
CH A
N – 12
CH B
N – 12
CH A
N – 11
CH B
N – 11
CH A
N – 10
CH B
N – 10
CH A
N – 9
CH B
N – 9
CH A
N – 8
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
VIN
CLK+
CLK–
DCO+
DCO–
D0+ (LSB)
PARALLEL
INTERLEAVED
MODE
D0– (LSB)
D13+ (MSB)
D13– (MSB)
tA
CH A
N – 12
CH B
N – 12
CH A
N – 11
CH B
N – 11
CH A
N – 10
CH B
N – 10
CH A
N – 9
CH B
N – 9
CH A
N – 8
CH A0
N – 12
CH A1
N – 12
CH A0
N – 11
CH A1
N – 11
CH A0
N – 10
CH A1
N – 10
CH A0
N – 9
CH A1
N – 9
CH A0
N – 8
D1+/0+ (LSB)
CHANNEL
MULTIPLEXED
MODE
CHANNEL A
D1–/D0– (LSB)
D13+/D12+ (MSB)
D13–/D12– (MSB)
CH A12
N – 12
CH A13
N – 12
CH A12
N – 11
CH A13
N – 11
CH A12
N – 10
CH A13
N – 10
CH A12
N – 9
CH A13
N – 9
CH A12
N – 8
CH B0
N – 12
CH B1
N – 12
CH B0
N – 11
CH B1
N – 11
CH B0
N – 10
CH B1
N – 10
CH B0
N – 9
CH B1
N – 9
CH B0
N – 8
D1+/D0+ (LSB)
CHANNEL
MULTIPLEXED
MODE
CHANNEL B
D1–/D0– (LSB)
D13+/D12+ (MSB)
D13–/D12– (MSB)
CH B12
N – 12
CH B13
N – 12
CH B12
N – 11
CH B13
N – 11
CH B12
N – 10
CH B13
N – 10
CH A12
N – 9
CH A13
N – 9
CH A12
N – 8
09975-
004
Figure 4. LVDS Modes for Data Output Timing
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