參數(shù)資料
型號： AD9644BCPZ-80
廠商： Analog Devices Inc
文件頁數(shù)： 17/44頁
文件大?。?/td> 0K
描述： IC ADC 14BIT 80MSPS 3V 48LFCSP
標準包裝： 1
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 460mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤
輸入數(shù)目和類型： 2 個差分，雙極
AD9644
Data Sheet
Rev. C | Page 24 of 44
CHANNEL/CHIP SYNCHRONIZATION
The AD9644 has a SYNC input that offers the user flexible
synchronization options for synchronizing the clock divider.
The clock divider sync feature is useful for guaranteeing synchro-
nized sample clocks across multiple ADCs. The input clock
divider can be enabled to synchronize on a single occurrence of
the SYNC signal or on every occurrence.
The SYNC input is internally synchronized to the sample clock;
however, to ensure that there is no timing uncertainty between
multiple parts, the SYNC input signal should be externally syn-
chronized to the input clock signal, meeting the setup and hold
times shown in Table 5. The SYNC input should be driven using
a single-ended CMOS-type signal.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 60 and Figure 61, the power dissipated by
the AD9644 varies with its sample rate (AD9644-80 shown).
The data in Figure 60 and Figure 61 was taken in JESD204A
serial output mode, using the same operating conditions as those
0
0.05
0.10
0.15
0.20
0.25
0
0.1
0.2
0.3
0.4
0.5
40
50
60
70
80
SU
PP
L
Y
CURRE
NT
(
A)
T
O
T
A
L
PO
W
ER
(W
)
ENCODE FREQUENCY (MSPS)
IAVDD
IDRVDD
TOTAL POWER
09180-
144
Figure 60. AD9644-80 Power and Current vs. Encode Frequency with fIN =
10.1 MHz
0.60
0.50
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.40
0.30
0.20
0.10
0
80
90
100
110
120
130
140
150
ENCODE FREQUENCY (MSPS)
TOTA
L
P
OWE
R
(
W)
S
UP
P
L
Y
CURRE
NT
(
A)
09180-
061
IAVDD
IDRVDD
TOTAL POWER
Figure 61. AD9644-155 Power and Current vs. Encode Frequency
with fIN = 10.1 MHz
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9644 is placed in power-down mode.
In this state, the ADC typically dissipates 15 mW. During power-
down, the output drivers are placed in a high impedance state.
Asserting the PDWN pin low returns the AD9644 to its normal
operating mode.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
clock, and JESD204A outputs . Internal capacitors are discharged
when entering power-down mode and then must be recharged
when returning to normal operation.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered and
the JESD204A outputs running when faster wake-up times are
required.
DIGITAL OUTPUTS
JESD204A Transmit Top Level Description
The AD9644 digital output complies with the JEDEC Standard
No. 204A (JESD204A), which describes a serial interface for
data converters. JESD204A uses 8B/10B encoding as well as
optional scrambling. K28.5 and K28.7 comma symbols are used
for frame synchronization and the K28.3 control symbol is used
for lane synchronization. The receiver is required to lock onto
the serial data stream and recover the clock with the use of a
PLL. For details on the output interface, users are encouraged to
refer to the JESD204A standard.
The JESD204A transmit block is used to multiplex data from
the two analog-to-digital converters onto two independent
JESD204A Links. Each JESD204A Link is considered a separate
instance of the JESD204A specification, has an independent
DSYNC signal, and contains one or more lanes. Note that the
JESD204 specification only allows one lane per link, while the
JESD204A specification adds multilane support through an
alignment procedure.
Each JESD204A Link is described according to the following
nomenclature:
S = samples transmitted/single converter/frame cycle
M = number of converters/converter device (link)
L = number of lanes/converter device (link)
N = converter resolution
N’ = total number of bits per sample
CF = number of control words/frame clock cycle/converter
device (link)
CS = number of control bits/conversion sample
K = number of frames per multiframe
HD = high density mode
F = octets/frame
C = control bit (overrange, overflow, underflow)
T = tail bit
SCR = scrambler enable/disable
FCHK = checksum
相關(guān)PDF資料
PDF描述
AD9648BCPZRL7-125 IC ADC 14BIT 125MSPS 64LFCSP
AD9649BCPZRL7-80 IC ADC 14BIT 80MSPS 32LFCSP
AD9653BCPZRL7-125 IC ADC 16BIT 125MSPS SRL 48LFCSP
AD9707BCPZRL7 IC DAC TX 14BIT 175MSPS 32-LFCSP
AD9709ASTZRL IC DAC 8BIT DUAL 125MSPS 48LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9644BCPZRL7-155 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14 Bit 155 Msps Dual 1.8V ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體:
AD9644BCPZRL7-80 功能描述:IC ADC 14BIT 80MSPS 3V 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極
AD9644CCPZ-80 功能描述:IC ADC 14BIT 80MSPS 3V 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極
AD9644CCPZRL7-80 功能描述:IC ADC 14BIT 80MSPS 3V 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極
AD9645 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual, 14-Bit, 80 MSPS/125 MSPS, Serial LVDS
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*