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| 型號： | AD9641BCPZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SRL 80MSPS 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
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Data Sheet
AD9641
Rev. B | Page 17 of 36
THEORY OF OPERATION
250 MHz, using appropriate low-pass or band-pass filtering at
the ADC inputs with little loss in ADC performance.
Synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD9641 are accomplished
using a 3-wire, SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9641 architecture consists of a front-end sample-and-
hold circuit, followed by a pipelined, switched-capacitor ADC.
The quantized outputs from each stage are combined into a final
14-bit result in the digital correction logic. The pipelined architec-
ture permits the first stage to operate on a new input sample
and the remaining stages to operate on the preceding samples.
Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution, flash ADC connected to a switched-capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next stage
in the pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage consists
of a flash ADC.
The input stage contains a differential sampling circuit that can
be ac- or dc-coupled in differential or single-ended modes. The
output staging block aligns the data, corrects errors, and passes the
data to the output buffers. The output buffers are powered from
a separate supply, allowing digital output noise to be separated
from the analog core. During power-down, the output buffers go
into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9641 is a differential switched-
capacitor circuit that has been designed for optimum performance
while processing a differential input signal.
The clock signal switches the input alternatively between sample
mode and hold mode (see Figure 48). When the input is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within 1/2 of a clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, any
shunt capacitors should be reduced because the input sample
capacitor is unbuffered. In combination with the driving source
impedance, the shunt capacitors limit the input bandwidth.
Refer to the AN-742 Application Note, Frequency Domain
Response of Switched-Capacitor ADCs; the AN-827 Application
Note, A Resonant Approach to Interfacing Amplifiers to Switched-
Capacitor ADCs; and the Analog Dialogue article, “Transformer-
information on this subject (refer to www.analog.com).
CPAR1
CPAR2
S
CFB
CS
BIAS
VIN+
H
VIN–
09
21
0-
03
0
Figure 48. Switched-Capacitor Input
For best dynamic performance, the source impedances driving
VIN+ and VIN should be matched, and the inputs should be
differentially balanced.
Input Common Mode
The analog inputs of the AD9641 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.5 × AVDD (or
0.9 V) is recommended for optimum performance. An on-board,
common-mode voltage reference is included in the design and
is available from the VCM pin. Using the VCM output to set the
input common mode is recommended. Optimum performance
is achieved when the common-mode voltage of the analog input
is set by the VCM pin voltage (typically, 0.5 × AVDD). The VCM
pin must be decoupled to ground by a 0.1 μF capacitor. This
decoupling capacitor should be placed close to the pin to minimize
the series resistance and inductance between the part and this
capacitor.
Differential Input Configurations
Optimum performance is achieved while driving the AD9641 in a
differential input configuration. For baseband applications, the
excellent performance and a flexible interface to the ADC.
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| AD9641BCPZRL7-155 | 制造商:Analog Devices 功能描述:14BIT 155MSPS ADC W/JESD204A - Tape and Reel 制造商:Analog Devices 功能描述:IC ADC 14BIT SRL 155MSPS 32LFCSP |
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| AD9642-210EBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 14 Bit 210 Msps 1.8V ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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