- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1988 > AD9641BCPZ-80 (Analog Devices Inc)IC ADC 14BIT SRL 80MSPS 32LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9641BCPZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/36頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SRL 80MSPS 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當(dāng)前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
Data Sheet
AD9641
Rev. B | Page 19 of 36
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9641.
The input full-scale range can be adjusted through the SPI port by
adjusting Bit 0 through Bit 4 of Register 0x18. These bits can be
used to change the full-scale value between 1.383 V p-p and
2.087 V p-p in 0.022 V steps, as shown in Table 17.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9641 sample clock inputs,
CLK+ and CLK, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK pins
by means of a transformer or a passive component configuration.
These pins are biased internally (see Figure 53) and require no
external bias. If the inputs are floated, the CLK pin is pulled low
to prevent spurious clocking.
AVDD
CLK+
4pF
CLK–
0.9V
0
9210
-03
5
Figure 53. Equivalent Clock Input Circuit
Clock Input Options
The AD9641 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section. The
minimum conversion rate of the AD9641 is 40 MSPS. At clock
rates below 40 MSPS, dynamic performance of the AD9641 can
degrade.
Figure 54 and Figure 55 show two preferred methods for clocking
the AD9641 (at clock rates up to 640 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
0.1F
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
Mini-Circuits
ADT1-1WT, 1:1Z
XFMR
092
10-
036
Figure 54. Transformer-Coupled Differential Clock (Up to 200 MHz)
0.1F
1nF
CLOCK
INPUT
1nF
50
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
09
21
0-
0
3
7
Figure 55. Balun-Coupled Differential Clock (Up to 640 MHz)
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 640 MHz, and the RF transformer is
recommended for clock frequencies from 40 MHz to 200 MHz.
The back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD9641 to approxi-
mately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9641 while
preserving the fast rise and fall times of the signal that are
critical to a low jitter performance.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
AD9520/AD9522 clock drivers offer excellent jitter performance.
100
0.1F
240
PECL DRIVER
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD95xx
ADC
0
921
0-
0
38
Figure 56. Differential PECL Sample Clock (Up to 640 MHz)
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 57. The AD9510/
performance.
100
0.1F
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD95xx
LVDS DRIVER
ADC
0
921
0-
0
39
Figure 57. Differential LVDS Sample Clock (Up to 640 MHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applica-
tions, the CLK+ pin should be driven directly from a CMOS gate,
and the CLK pin should be bypassed to ground with a 0.1 μF
capacitor (see Figure 58).
OPTIONAL
100
0.1F
50*
*50 RESISTOR IS OPTIONAL.
CLK–
CLK+
VCC
1k
CLOCK
INPUT
AD95xx
CMOS DRIVER
ADC
09210-
040
Figure 58. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9644BCPZ-80 | IC ADC 14BIT 80MSPS 3V 48LFCSP |
| AD9648BCPZRL7-125 | IC ADC 14BIT 125MSPS 64LFCSP |
| AD9649BCPZRL7-80 | IC ADC 14BIT 80MSPS 32LFCSP |
| AD9653BCPZRL7-125 | IC ADC 16BIT 125MSPS SRL 48LFCSP |
| AD9707BCPZRL7 | IC DAC TX 14BIT 175MSPS 32-LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9641BCPZRL7-155 | 制造商:Analog Devices 功能描述:14BIT 155MSPS ADC W/JESD204A - Tape and Reel 制造商:Analog Devices 功能描述:IC ADC 14BIT SRL 155MSPS 32LFCSP |
| AD9641BCPZRL7-80 | 功能描述:14 Bit Analog to Digital Converter 1 Input 1 Pipelined 32-LFCSP-WQ (5x5) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 位數(shù):14 采樣率（每秒）:80M 輸入數(shù):1 輸入類型:差分 數(shù)據(jù)接口:JESD204A 配置:S/H-ADC 無線電 - S/H:ADC:1:1 A/D 轉(zhuǎn)換器數(shù):1 架構(gòu):管線 參考類型:內(nèi)部 電壓 - 電源，模擬:1.7 V ~ 1.9 V 電壓 - 電源，數(shù)字:1.7 V ~ 1.9 V 特性:- 工作溫度:-40°C ~ 85°C 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標(biāo)準(zhǔn)包裝:1,500 |
| AD9642 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC) |
| AD9642-170EBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 14 Bit 170 Msps 1.8V ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9642-210EBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 14 Bit 210 Msps 1.8V ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。