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| 型號(hào)： | AD9627ABCPZ11-150 |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 21/72頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 11BIT 150MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 11 |
| 采樣率（每秒）： | 150M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 890mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤(pán) |
| 輸入數(shù)目和類(lèi)型： | 4 個(gè)單端，單極；2 個(gè)差分，單極 |
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AD9627-11
Rev. B | Page 28 of 72
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9627-11. Power supplies for clock drivers should be sepa-
rated from the ADC output driver supplies to avoid modulating
the clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or some other
method), it should be retimed by the original clock at the last step.
Refer to Application Note AN-501 and Application Note AN-756
(see www.analog.com) for more information about jitter perform-
ance as it relates to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 63 and Figure 64, the power dissipated by
the AD9627-11 is proportional to its sample rate. In CMOS
output mode, the digital power dissipation is determined
primarily by the strength of the digital drivers and the load on
each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (24, in the case of the
AD9627-11, with the fast detect output pins disabled).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency of fCLK/2. In practice, the DRVDD current
is established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 63 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
TOT
A
L
P
O
W
E
R
(W)
S
U
PP
L
Y
C
U
R
EN
T
(
A
)
SAMPLE RATE (MSPS)
0
0.1
0.2
0.3
0.4
0.5
IAVDD
IDVDD
0.25
0
0.50
0.75
1.00
1.25
0
255075
100
125
150
TOTAL POWER
07
05
4-
06
3
IDRVDD
Figure 63. AD9627-11-150 Power and Current vs. Sample Rate
TOT
A
L
P
O
W
E
R
(W)
S
UP
P
L
Y
CU
RRE
N
T
(
A)
SAMPLE RATE (MSPS)
0
0.1
0.2
0.3
0.4
IDVDD
IDRVDD
0.25
0
0.50
0.75
1.00
025
50
75
100
TOTAL POWER
07
05
4-
06
4
IAVDD
Figure 64. AD9627-11-105 Power and Current vs. Sample Rate
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9627-11 is placed in power-down
mode. In this state, the ADC typically dissipates 2.5 mW. During
power-down, the output drivers are placed in a high impedance
state. Asserting the PDWN pin low returns the AD9627-11 to
its normal operating mode. Note that PDWN is referenced to
the digital output driver supply (DRVDD) and should not exceed
that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section for more details.
DIGITAL OUTPUTS
The AD9627-11 output drivers can be configured to interface
with 1.8 V to 3.3 V CMOS logic families by matching DRVDD
to the digital supply of the interfaced logic. The AD9627-11 can
also be configured for LVDS outputs using a DRVDD supply
voltage of 1.8 V.
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause current glitches on
the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
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