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| 型號： | AD9600ABCPZ-125 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/72頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 125MSPS 64LFCSP |
| 標準包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 800mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，單極 |
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AD9600
Rev. B | Page 34 of 72
the value of the accumulator is reset to the first input sample
signal power, and the accumulation continues with the
subsequent input samples.
Figure 68 illustrates the rms magnitude monitoring logic.
0
690
9-
0
92
SIGNAL MONITOR
HOLDING
REGISTER (SMR)*
ACCUMULATOR
TO
MEMORY
MAP/SPORT
FROM
MEMORY
MAP
FROM
INPUT
PORTS
LOAD
CLEAR
LOAD
IS COUNT = 1?
DOWN
COUNTER
SIGNAL MONITOR
PERIOD REGISTER
*THIS IS AN INTERNAL REGISTER. IT IS NOT IN THE REGISTER
MAP AND CANNOT BE ACCESSED BY USERS.
Figure 68. ADC Input RMS Magnitude Monitoring Block Diagram
For rms magnitude mode, the value in the signal monitor result
(SMR) register is a 20-bit fixed-point number. The following
equation can be used to determine the rms magnitude in decibels
full scale (dBFS) from the MAG value in the register:
RMS Magnitude = 20 log
[]
)
(
log
20
2
log
10
2
SMP
ceil
SMP
MAG
where if the signal monitor period (SMP) is a power of 2, the
second term in the equation becomes 0.
For ms magnitude mode, the value in the SMR is a 20-bit fixed-
point number. The following equation can be used to determine
the ms magnitude in decibels full scale (dBFS) from the MAG
value in the register:
MS Magnitude = 10 log
[]
)
(
log
20
2
log
10
2
SMP
ceil
SMP
MAG
where if the SMP is a power of 2, the second term in the
equation becomes 0.
THRESHOLD CROSSING MODE
In the threshold crossing mode of operation, the magnitude of
the input port signal is monitored over a programmable period
(determined by SMPR) to count the number of times it crosses a
certain programmable threshold value. This mode is set by
programming Logic 1x (where x is a don’t care bit) in the signal
monitor mode bits of the signal monitor control register
(Address 0x112) or by setting the threshold crossing output
enable bit in the signal monitor SPORT control register
(Address 0x111). Before activating this mode, the user needs to
program the 24-bit signal monitor period register (Address 0x113
to Address 0x115) and the 13-bit fine upper threshold register
(Address 0x106 and Address 0x107) for each individual input
port. The same fine upper threshold register is used for both
signal monitoring and gain control (see the ADC Overrange
and Gain Control section).
After entering this mode, the value in the SMPR is loaded
into a monitor period timer and the countdown is started. The
magnitude of the input signal is compared with the previously
programmed fine upper threshold register on each input clock
cycle. If the input signal has a magnitude greater than the value
set in the fine upper threshold register, the value in the internal
count register (not accessible to the user) is incremented by 1.
The initial value of the internal count register is set to 0. The
comparison and incrementing of this value continues until the
monitor period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the value
in the internal count register is transferred to the signal monitor
holding register (not accessible to the user), which can be read
through the SPI port or output through the SPORT serial port.
The monitor period timer is reloaded with the value in the SMPR,
and the countdown is restarted. The internal count register is
also cleared to a value of 0. Figure 69 illustrates the threshold
crossing logic. The value in the SMR register is the number of
samples that have a magnitude greater than the fine upper
threshold register.
06
90
9-
0
46
SIGNAL MONITOR
HOLDING
REGISTER (SMR)*
COMPARE
A > B
COMPARE
A > B
TO
MEMORY
MAP/SPORT
FROM
MEMORY
MAP
FROM
MEMORY
MAP
FROM
INPUT
PORTS
LOAD
CLEAR
LOAD
IS COUNT = 1?
DOWN
COUNTER
SIGNAL MONITOR
PERIOD REGISTER
B
A
*THIS IS AN INTERNAL REGISTER. IT IS NOT IN THE REGISTER
MAP AND CANNOT BE ACCESSED BY USERS.
FINE UPPER
THRESHOLD
REGISTER
Figure 69. ADC Input Threshold Crossing Block Diagram
ADDITIONAL CONTROL BITS
For additional flexibility in the signal monitoring process, two
control bits are provided in the signal monitor control register
(Address 0x112). They are the signal monitor enable bit and the
complex power calculation mode enable bit.
Signal Monitor Enable Bit
The signal monitor enable bit, located in Bit 0 of Register 0x112,
enables operation of the signal monitor block. If the signal monitor
function is not needed in a particular application, this bit should
be cleared (default) to conserve power.
Complex Power Calculation Mode Enable Bit
When this bit is set, the part assumes that Channel A is digitizing
the I data and Channel B is digitizing the Q data for a complex
input signal (or vice versa). In this mode, the power reported is
equal to
2
Q
I +
This result is presented in the signal monitor DC value Channel A
register (Address 0x10D and Address 0x10E) if the signal monitor
mode bits are set to 00. The signal monitor DC value Channel B
register (Address 0x10F and Address 0x110) continues to compute
the Channel B value.
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