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| 型號： | AD9600ABCPZ-125 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 125MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 800mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，單極 |
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AD9600
Rev. B | Page 28 of 72
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 63, the power dissipated by the AD9600 is
proportional to its sample rate. In CMOS output mode, the
digital power dissipation is determined primarily by the
strength of the digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
N
f
C
V
I
CLK
LOAD
DRVDD
×
=
where N is the number of output bits (22 in the case of AD9600
with the fast detect output pins disabled).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, fCLK/2. In practice, the DRVDD current is
established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal. Reducing the capacitive load presented
to the output drivers can minimize digital power consumption.
The data in Figure 63 was taken with the same operating
conditions as the Typical Performance Characteristics, with a
5 pF load on each output driver.
TOT
A
L
P
O
W
E
R
(W
)
S
UP
P
L
Y
CU
RRE
NT
(
A
)
ENCODE (MSPS)
0
0.1
0.2
0.3
0.4
0.5
IAVDD
IDVDD
IDRVDD
0.25
0
0.50
0.75
1.00
1.25
0
25
50
75
100
125
150
TOTAL POWER
06
90
9-
03
8
Figure 63. AD9600-150 Power and Current vs. Sample Rate
TO
T
A
L
P
O
W
E
R
(
W
)
S
UP
P
L
Y
C
URRE
NT
(A)
ENCODE (MSPS)
0
0.1
0.2
0.3
0.4
0.5
IAVDD
IDVDD
IDRVDD
0.25
0
0.50
0.75
1.00
1.25
0
25
50
75
100
125
TOTAL POWER
06
90
9-
03
9
Figure 64. AD9600-125 Power and Current vs. Sample Rate
TOT
A
L
P
O
W
E
R
(W
)
SU
PPL
Y
C
U
R
EN
T
(A
)
ENCODE (MSPS)
0100
75
50
25
0
0.25
0.50
0.75
1.00
0
0.1
0.2
0.3
0.4
06
90
9-
9
99
IAVDD
IDVDD
IDRVDD
TOTAL POWER
Figure 65. AD9600-105 Power and Current vs. Sample Rate
By asserting the PDWN mode (either through the SPI port or
by asserting the PDWN pin high), the AD9600 is placed into
power-down mode. In this state, the ADC typically dissipates
2.5 mW. During power-down, the output drivers are placed in a
high impedance state. Asserting the PDWN pin low returns the
AD9600 to its normal operating mode. Note that PDWN is
referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and must be recharged when returning to
normal operation. As a result, the wake-up time is related to the
time spent in power-down mode: shorter power-down cycles
result in proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
into power-down or standby mode. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map
Register Description section for more details.
DIGITAL OUTPUTS
The AD9600 output drivers can be configured to interface with
1.8 V to 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic.
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies and may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when
operating in the external pin mode (see Table 12). As detailed in
the Memory Map Register Description section, the data format
can be selected for offset binary, twos complement, or gray code
when using the SPI control.
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| AD9600ABCPZ-150 | 功能描述:IC ADC 10BIT 150MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9600BCPZ-105 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 105Msps 10-bit Parallel/LVDS 64-Pin LFCSP EP |
| AD9600BCPZ-125 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 125Msps 10-bit Parallel/LVDS 64-Pin LFCSP EP |
| AD9600BCPZ-150 | 制造商:Analog Devices 功能描述: |
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