參數(shù)資料
型號(hào)： AD9600ABCPZ-125
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/72頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT 125MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 10
采樣率（每秒）： 125M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 800mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸入數(shù)目和類型： 4 個(gè)單端，單極；2 個(gè)差分，單極
AD9600
Rev. B | Page 26 of 72
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve the thermal drift
characteristics. Figure 54 shows the typical drift characteristics
of the internal reference in 1.0 V mode.
2.5
–2.5
–40
TEMPERATURE (°C)
R
EF
ER
EN
C
E
VO
L
T
A
G
E
ER
R
O
R
(
m
V
)
2.0
1.5
1.0
0
–0.5
–1.0
–1.5
–2.0
–20
0
2040
6080
0
6
90
9-
2
99
Figure 54. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 15). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9600 sample clock inputs
(CLK+ and CLK) should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK pins
via a transformer or capacitors. These pins are biased internally
(see Figure 55) and require no external bias.
1.2V
CLK+
AVDD
CLK–
2pF
06
909
-0
23
Figure 55. Equivalent Clock Input Circuit
Clock Input Options
The AD9600 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, the jitter of the clock
source is of the most concern, as described in the Jitter
Figure 56 and Figure 57 show preferred methods for clocking the
AD9600 (at clock rates of up to 625 MHz). A low jitter clock source
is converted from a single-ended signal to a differential signal
using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock
frequencies between 125 MHz and 625 MHz, and the RF
transformer is recommended for clock frequencies from 10 MHz
to 200 MHz. The back-to-back Schottky diodes across the
secondary transformer or balun limit clock excursions into the
AD9600 to approximately 0.8 V p-p differential.
This helps prevent the large voltage swings of the clock from
feeding through to other portions of the AD9600 while
preserving the fast rise and fall times of the signal that are
critical to low jitter performance.
0.1F
SCHOTTKY
DIODES:
HSMS2822
CLK+
50
100
CLK–
CLK+
ADC
AD9600
Mini-Circuits
ADT1-1WT, 1:1Z
XFMR
069
09-
0
24
Figure 56. Transformer-Coupled Differential Clock (up to 200 MHz)
0.1F
1nF
CLK+
1nF
50
CLK–
CLK+
ADC
AD9600
SCHOTTKY
DIODES:
HSMS2822
06
90
9-
05
7
Figure 57. Balun-Coupled Differential Clock (up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
AD9513/AD9514/AD9515 family of clock drivers offers excellent
jitter performance.
100
0.1F
240
240
PECL
DRIVER
AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515
50k
50k
CLK–
CLK+
ADC
AD9600
CLK+
CLK–
0
690
9-
0
25
Figure 58. Differential PECL Sample Clock (up to 150 MSPS)
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins as shown in Figure 59. The AD9510/
drivers offer excellent jitter performance.
100
0.1F
50k
LVDS
DRIVER
50k
CLK–
CLK+
CLK–
CLK+
ADC
AD9600
AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515
06
90
9-
0
26
Figure 59. Differential LVDS Sample Clock (up to 150 MSPS)
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參數(shù)描述
AD9600ABCPZ-150 功能描述:IC ADC 10BIT 150MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
AD9600BCPZ-105 制造商:Analog Devices 功能描述:ADC Dual Pipelined 105Msps 10-bit Parallel/LVDS 64-Pin LFCSP EP
AD9600BCPZ-125 制造商:Analog Devices 功能描述:ADC Dual Pipelined 125Msps 10-bit Parallel/LVDS 64-Pin LFCSP EP
AD9600BCPZ-150 制造商:Analog Devices 功能描述:
AD9601 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 200 MSPS/250 MSPS 1.8 V Analog-to-Digital Converter
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