- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9674 > AD9553BCPZ (Analog Devices Inc)IC INTEGER-N CLCK GEN 32LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9553BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTEGER-N CLCK GEN 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率轉(zhuǎn)換器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，GPON，SONET/SHD，T1/E1 |
| 輸入： | CMOS，LVDS，晶體 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 810MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP（5x5） |
| 包裝： | 托盤 |
| 配用： | AD9553/PCBZ-ND - BOARD EVAL FOR AD9553 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
AD9553
Rev. A | Page 16 of 44
THEORY OF OPERATION
A[3:0]
REGISTER BANK
OUTPUT MODE/
SERIAL PORT
PRECONFIGURED
DIVIDER SETTINGS
REFA
XTAL
Y[5:0]
4
6
3
XTAL
VCO
AD9553
OUT1
3350MHz
TO
4050MHz
LOCKED
FILTER
2
N
P
F
D
OUT2
2
20
3
10
P0
P1
P2
P0
P1
DN
UP
3
SPI CTRL
3
×2
FDBK
REFERENCE
SWITCHOVER
CONTROL
CLOCK
MUX
CLOCK MUX
HOLD
REF
SEL
DET
A
DET
B
DET
XO
SEL REFB
DCXO
CTRL
TEST
1 0
0
1
0
1
0
1
RA, ×2A, ÷5A
RB, ×2B, ÷5B
RXO, DCXO CTRL
N, P0, P1, P2
REF SEL
TEST
REF DIFF
REF
DIFF
÷5
0
1
÷5A
÷5
0
1
÷5B
REFB/REFA
XO
FPFD
PLL
14
DET
DET A
0
1
÷RA
÷N
×2A
RA
×2
14
DET
DET B
0
1
÷RB
×2B
RB
×2
14
DET
DET XO
÷RXO
RXO
TUNING
CONTROL
UP/2
FPFD/2
FDBK/2
XO
LOCK
DETECT
OUTPUT
MODE
CONTROL
5 TO 11
LOOP
FILTER
CHARGE
PUMP
08565-
101
Figure 27. Detailed Block Diagram
OVERVIEW
The AD9553 can receive up to two input reference clocks, REFA
and REFB. Both input clock paths include an optional divide-by-5
(÷5) prescaler, an optional ×2 frequency multiplier, and a 14-bit
programmable divider. Alternatively, the user can program the
device to operate with one differential input clock (instead of
two single-ended input clocks) via the serial I/O port. In the
differential operating mode, the REFB path is inactive.
The AD9553 also has a dedicated XTAL input for direct connec-
tion of an optional 25 MHz crystal resonator. This allows for a
backup clock signal useful for holdover operation in case both
input references fail. The XTAL clock path includes a fixed ×2
frequency multiplier and a 14-bit programmable divider.
The AD9553 includes a switchover control block that auto-
matically handles switching from REFA to REFB (or vice versa)
in the event of a reference failure. If both REFA and REFB fail,
however, then the switchover control block automatically enters
holdover mode by selecting the XTAL clock signal (assuming
the presence of a crystal resonator at the XTAL input).
Generally, the clock signals that appear at the input to the clock
multiplexer (see Figure 27) all operate at the same frequency.
Thus, the frequency at the input to the PLL (FPFD in Figure 27)
is the same regardless of the signal selected by the clock multi-
plexer. The PLL converts FPFD to a frequency within the operating
range of the VCO (3.35 GHz to 4.05 GHz) based on the value of
the feedback divider (N). The VCO prescaler (P0) reduces the
VCO output frequency by an integer factor of 5 to 11, resulting in
an intermediate frequency in the range of 305 MHz to 810 MHz.
The 10-bit P1 and P2 dividers can further reduce the P0 output
frequency to yield the final output clock frequencies at OUT1
and OUT2, respectively.
Thus, the frequency translation ratio from the reference input
to the output depends on the selection of the ÷5 prescalers; the
×2 frequency multipliers; the values of the three R dividers; the
N divider; and the P0, P1, and P2 dividers. These parameters are
set automatically via the preconfigured divider settings per the Ax
and Yx pins (see the Preset Frequencies section). Alternatively, the
user can custom program these parameters via the serial I/O port
(see the Serial Control Port and Register Map sections), which allows
the device to accommodate custom frequency translation ratios.
PRESET FREQUENCIES
The frequency selection pins (A3 to A0 and Y5 to Y0) allow the
user to hardwire the device for preset input and output frequencies
based on the pin logic states (see Figure 27). The pins decode
ground or open connections as Logic 0 or Logic 1, respectively.
To have access to the device control registers via the SPI port, the
user must select Pin Y5 to Pin Y0 = 000000 and/or Pin A3 to
Pin A0 = 0000. Doing so causes Pin 12 through Pin 14 to function
as SPI port control pins instead of output mode control pins (see
the Output Driver Mode Control section). Note that after selecting
SPI mode, the user must write a Logic 1 to Bit 0 of Register 0x32
and Register 0x34 to enable the registers as the source of the OUT1
and OUT2 mode control bits (see Figure 31 and the Output Driver
Mode Control section).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MS27467T25F2P | CONN PLUG 100POS STRAIGHT W/PINS |
| AD9550BCPZ | IC INTEGER-N TRANSLATOR 32-LFCSP |
| AD9573ARUZ | IC PCI CLCOK GEN 25MHZ 16TSSOP |
| MS3452W24-22PW | CONN RCPT 4POS BOX MNT W/PINS |
| MS3452W24-22P | CONN RCPT 4POS BOX MNT W/PINS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9553BCPZ-REEL7 | 功能描述:IC INTEGER-N CLCK GEN 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9554/PCBZ | 功能描述:AD9554 - Timing, Clock Generator Evaluation Board 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 主要用途:計時，時鐘發(fā)生器 嵌入式:- 使用的 IC/零件:AD9554 主要屬性:- 輔助屬性:LED 狀態(tài)指示器 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| AD9554-1/PCBZ | 功能描述:AD9554-1 - Timing, Clock Generator Evaluation Board 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 主要用途:計時，時鐘發(fā)生器 嵌入式:- 使用的 IC/零件:AD9554-1 主要屬性:- 輔助屬性:LED 狀態(tài)指示器 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| AD9554-1BCPZ | 功能描述:IC PLL CLOCK GEN 4OUT 72LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):有效 PLL:是 主要用途:以太網(wǎng)，SONET/SDH，Stratum 輸入:CMOS，LVDS 輸出:HCSL，LVDS，LVPECL 電路數(shù):1 比率 - 輸入:輸出:4：4 差分 - 輸入:輸出:是/是 頻率 - 最大值:942MHz 電壓 - 電源:1.4 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-WFQFN 裸焊盤，CSP 供應(yīng)商器件封裝:56-LFCSP-WQ（8x8） 標(biāo)準(zhǔn)包裝:1 |
| AD9554-1BCPZ-REEL7 | 功能描述:IC PLL CLOCK GEN 4OUT 72LFCSP 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 PLL:是 主要用途:以太網(wǎng)，SONET/SDH，Stratum 輸入:CMOS，LVDS 輸出:HCSL，LVDS，LVPECL 電路數(shù):1 比率 - 輸入:輸出:4：4 差分 - 輸入:輸出:是/是 頻率 - 最大值:942MHz 電壓 - 電源:1.4 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-WFQFN 裸焊盤，CSP 供應(yīng)商器件封裝:56-LFCSP-WQ（8x8） 標(biāo)準(zhǔn)包裝:750 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。