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參數(shù)資料
| 型號： | AD9553BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTEGER-N CLCK GEN 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率轉(zhuǎn)換器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，GPON，SONET/SHD，T1/E1 |
| 輸入： | CMOS，LVDS，晶體 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 810MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP（5x5） |
| 包裝： | 托盤 |
| 配用： | AD9553/PCBZ-ND - BOARD EVAL FOR AD9553 |
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AD9553
Rev. A | Page 26 of 44
JITTER TOLERANCE
Jitter tolerance is the ability of the AD9553 to maintain lock in
the presence of sinusoidal jitter. The AD9553 meets the input
jitter tolerance mask per Telcordia GR-253-CORE (see Figure 32).
The acceptable jitter tolerance is the region above the mask. The
trace showing the performance of the AD9553 in Figure 32
represents the limitations of the test equipment because the
AD9553 did not indicate loss of lock, even with the test
equipment injecting its maximum jitter level.
1k
0.1
1
10
100
0.01
0.1
1
10
100
1k
10k
IN
P
U
T
J
ITTE
R
A
M
P
LITU
D
E
(
U
L
PP
)
JITTER FREQUENCY (kHz)
08565-
030
AD9553
MASK
Figure 32. Jitter Tolerance
OUTPUT/INPUT FREQUENCY RELATIONSHIP
The frequency at OUT1 and OUT2 depends on the frequency at
the input to the PLL, the PLL feedback divider value (N), and the
output divider values (P0, P1, and P2). The equations that define
the frequency at OUT1 and OUT2 (fOUT1 and fOUT2, respectively)
are as follows:
×
=
1
0
1
P
N
FPFD
fOUT
×
=
2
0
2
P
N
FPFD
fOUT
where:
FPFD is the frequency at the reference input of the PFD.
N is the feedback divider value.
P0 is the VCO prescaler divider value.
P1 is the OUT1 divider value.
P2 is the OUT2 divider value.
The operating frequency range of the PFD places a limitation
on FPFD as follows:
13.3 kHz ≤ FPFD ≤ 100 MHz
Note that for applications using the frequency selection pins in
conjunction with the XTAL input for the holdover function, the
maximum value of FPFD is 50 MHz (twice the 25 MHz default
crystal frequency).
FPFD depends on the input frequency to the AD9553, the
configuration of the multiplexers for the ÷5 prescaler and ×2
frequency multiplier, and the value of the RX divider (either RA,
RB, or RXO) as follows:
X
R
K
f
FPFD
×
=
where:
fX is equal to fREFA, fREFB, or fXTAL.
K is the scale factor per Table 22.
FPFD is the frequency at the input to the phase frequency
detector.
Table 22. K as a Function of Input Multiplexer Configuration
Input
÷5
×2
K
REFA
Bypassed
1
Active
Bypassed
1/5
Bypassed
Active
2
Active
2/5
REFB
Bypassed
1
Active
Bypassed
1/5
Bypassed
Active
2
Active
2/5
XTAL
2
1 N/A means not applicable.
This leads to the complete frequency translation formula
×
=
1
0
1
P
N
R
K
f
X
OUT
×
=
2
0
2
P
N
R
K
f
X
OUT
Specific numeric constraints apply as follows. Note that the
symbol ∈ indicates that the constraint is an element of one in
the series from the list within the curly brackets.
K
∈
2
,1
,
5
2
,
5
1
KX∈ {1, 2, …, 16,384}
N∈ {32, 33, …, 1,048,576}
P0∈ {5, 6, …, 11}
P1∈ {1, 2, …, 63}
P2∈ {1, 2, …, 63}
Additional constraints apply. One constraint is related to the
VCO and the other to the ×2 frequency multipliers in the REFA
and REFB paths. The VCO constraint is a consequence of its
limited bandwidth. However, the ×2 frequency multiplier
constraint only applies when the ÷5 prescalers are bypassed, but
it also requires that RA and RB are large enough to satisfy the
FPFD constraint. The additional constraints are as follows:
3350 MHz ≤ fOUT1 × P0 × P1 ≤ 4050 MHz
3350 MHz ≤ fOUT2 × P0 × P2 ≤ 4050 MHz
fREFA/REFB ≤ 125 MHz (×2 multiplier with ÷5 bypassed)
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| AD9553BCPZ-REEL7 | 功能描述:IC INTEGER-N CLCK GEN 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9554/PCBZ | 功能描述:AD9554 - Timing, Clock Generator Evaluation Board 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 主要用途:計時，時鐘發(fā)生器 嵌入式:- 使用的 IC/零件:AD9554 主要屬性:- 輔助屬性:LED 狀態(tài)指示器 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| AD9554-1/PCBZ | 功能描述:AD9554-1 - Timing, Clock Generator Evaluation Board 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 主要用途:計時，時鐘發(fā)生器 嵌入式:- 使用的 IC/零件:AD9554-1 主要屬性:- 輔助屬性:LED 狀態(tài)指示器 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| AD9554-1BCPZ | 功能描述:IC PLL CLOCK GEN 4OUT 72LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):有效 PLL:是 主要用途:以太網(wǎng)，SONET/SDH，Stratum 輸入:CMOS，LVDS 輸出:HCSL，LVDS，LVPECL 電路數(shù):1 比率 - 輸入:輸出:4：4 差分 - 輸入:輸出:是/是 頻率 - 最大值:942MHz 電壓 - 電源:1.4 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-WFQFN 裸焊盤，CSP 供應(yīng)商器件封裝:56-LFCSP-WQ（8x8） 標(biāo)準(zhǔn)包裝:1 |
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