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參數(shù)資料
| 型號： | AD9553BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTEGER-N CLCK GEN 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率轉(zhuǎn)換器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，GPON，SONET/SHD，T1/E1 |
| 輸入： | CMOS，LVDS，晶體 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 810MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP（5x5） |
| 包裝： | 托盤 |
| 配用： | AD9553/PCBZ-ND - BOARD EVAL FOR AD9553 |
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AD9553
Rev. A | Page 20 of 44
A[3:0]
4
SPI/OM[2:0]
3
0
1
0
3
0
1
FUNCTION
ABC BITS
0
1
FUNCTION
XYZ BITS
ENABLE SPI CONTROL
OF OUTPUT MODE
ENABLE SPI CONTROL
OF OUTPUT ABC BITS
ENABLE SPI CONTROL
OF FUNCTIONING XYZ
OUTPUT
MODE
CONTROL
FUNCTION
BITS
REGISTER MAP
FUNCTION
MUXES
SPI CONTROLLER
FREQUENCY
SELECTION
PINS DECODER
OUTPUT
MODE
CONTROL
DECODER
OUTPUT MODE
CONTROL
FUNCTION
ABC
FUNCTION
XYZ
Y[5:0]
6
3
SPI MODE
08565-
100
Figure 28. Control Mode Diagram
Although the SPI and pin control modes are functionally
independent, it is possible to mix the control modes. For
example, suppose that pin control satisfies all of the require-
ments for an application except for the value of the P2 divider
(which is associated with OUT2). The user could do the
following:
Activate SPI mode via the frequency selection pins.
Program the desired P0, P1, and P2 values in the register
map (Register 0x15 to Register 0x18).
Set the enable SPI control bit for the output dividers
(Register 0x14[2] = 1).
Calibrate the VCO by enabling SPI control of VCO
calibration (Register 0x0E[2] = 1), then issue a calibrate
command (Register 0x0E[7] = 1). Be sure to program the
N divider, R dividers, ÷5 dividers, and ×2 multipliers to the
values defined by the Ax and Yx pin settings prior to cali-
brating the VCO.
Restore the original settings to the frequency selection pins
to invoke the desired frequency selection.
In this way, the function muxes that control P0, P1, and P2 select
the appropriate register bits as the source for controlling the
dividers, while all the other function muxes select the pin decoders
as the source for controlling the other functions. Note that the
dividers remain under register control until the user activates
SPI mode and writes Register 0x14[2] = 0, thereby causing the
function mux to use the frequency selection pins decoder as the
source for controlling the dividers, instead of the register map.
DESCRIPTION OF FUNCTIONAL BLOCKS
Reference Inputs
The default configuration of the AD9553 provides up to two
single-ended input clock receivers, REFA and REFB, which are
high impedance CMOS inputs. In applications that require redun-
dant reference clocks with switchover capability, REFA is the
primary reference and REFB the secondary reference. Alternatively,
the user can configure the input (via the serial I/O port) as a
single differential receiver. In this case, the REFB input func-
tions as REFA (the complementary input of REFA). Note that
in this configuration the device operates with only one reference
input clock, eliminating the need for switchover functionality.
XTAL Input
The AD9553 accepts an optional 25 MHz crystal resonator
connected across the XTAL pins. Alternatively, it accepts a
single-ended clock source (CMOS compatible) connected to
either one of the XTAL input pins (in this case, the unused
input remains floating). Unless otherwise programmed, the
device expects the crystal to have a specified load capacitance
of 10 pF (default). The AD9553 provides the necessary load
capacitance internally. The internal load capacitance consists
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| AD9553BCPZ-REEL7 | 功能描述:IC INTEGER-N CLCK GEN 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9554/PCBZ | 功能描述:AD9554 - Timing, Clock Generator Evaluation Board 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 主要用途:計(jì)時(shí)，時(shí)鐘發(fā)生器 嵌入式:- 使用的 IC/零件:AD9554 主要屬性:- 輔助屬性:LED 狀態(tài)指示器 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| AD9554-1/PCBZ | 功能描述:AD9554-1 - Timing, Clock Generator Evaluation Board 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 主要用途:計(jì)時(shí)，時(shí)鐘發(fā)生器 嵌入式:- 使用的 IC/零件:AD9554-1 主要屬性:- 輔助屬性:LED 狀態(tài)指示器 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| AD9554-1BCPZ | 功能描述:IC PLL CLOCK GEN 4OUT 72LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):有效 PLL:是 主要用途:以太網(wǎng)，SONET/SDH，Stratum 輸入:CMOS，LVDS 輸出:HCSL，LVDS，LVPECL 電路數(shù):1 比率 - 輸入:輸出:4：4 差分 - 輸入:輸出:是/是 頻率 - 最大值:942MHz 電壓 - 電源:1.4 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-WFQFN 裸焊盤，CSP 供應(yīng)商器件封裝:56-LFCSP-WQ（8x8） 標(biāo)準(zhǔn)包裝:1 |
| AD9554-1BCPZ-REEL7 | 功能描述:IC PLL CLOCK GEN 4OUT 72LFCSP 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 PLL:是 主要用途:以太網(wǎng)，SONET/SDH，Stratum 輸入:CMOS，LVDS 輸出:HCSL，LVDS，LVPECL 電路數(shù):1 比率 - 輸入:輸出:4：4 差分 - 輸入:輸出:是/是 頻率 - 最大值:942MHz 電壓 - 電源:1.4 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-WFQFN 裸焊盤，CSP 供應(yīng)商器件封裝:56-LFCSP-WQ（8x8） 標(biāo)準(zhǔn)包裝:750 |
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