參數(shù)資料
型號: AD9523-1BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 45/60頁
文件大?。?/td> 0K
描述: IC INTEGER-N CLCK GEN 72LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 時鐘/頻率發(fā)生器,扇出緩沖器(分配),多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),光纖通道,SONET/SDH
輸入: CMOS
輸出: HSTL,LVCMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:14
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1GHz
電源電壓: 1.768 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 72-LFCSP
包裝: 托盤
配用: AD9523/PCBZ-ND - BOARD EVAL FOR AD9523
AD9523-1
Rev. B | Page 5 of 60
POWER DISSIPATION
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER DISSIPATION
Does not include power dissipated in termination resistors
Typical Configuration
898
984.7
mW
Clock distribution outputs running as follows: 7 LVPECL at 122.88 MHz,
3 LVDS (3.5 mA) at 61.44 MHz, 3 LVDS (3.5 mA) at 245.76 MHz, 1 single-
ended CMOS 10 pF load at 122.88 MHz, 1 differential input reference
at 30.72 MHz; fVCXO = 122.88 MHz, fVCO = 2949.12 MHz, VCO Divider M1
at 3, and VCO Divider M2 is off; PLL2 BW = 530 kHz
PD, Power-Down
74
98.2
mW
PD pin pulled low, with typical configuration conditions
INCREMENTAL POWER DISSIPATION
Base Typical Configuration
393
434.7
mW
Absolute total power with clock distribution; 1 LVPECL output (OUT0)
running at 122.88 MHz; 1 differential input reference at 30.72 MHz;
fVCXO = 122.88 MHz, fVCO = 2949.12 MHz, VCO Divider M1 at 3; VCO
Divider M2 is off
Switched to One Input,
Reference Single-Ended Mode
28.5
8
mW
Running at 30.72 MHz
Switched to Two Inputs,
Reference Differential Mode
26
44.6
mW
Running at 30.72 MHz
Switched to Two Inputs,
Reference Single-Ended Mode
27.5
5.1
mW
Running at 30.72 MHz
VCO Divider M2
76
88.3
mW
Incremental power increase VCO Divider M2 (OUT4) from base typical
Output Distribution, Driver On
Incremental power increase (OUT1) from base typical
LVDS Mode
3.5 mA
29
34.8
mW
Single 3.5 mA LVDS output at 122.88 MHz
88
105.6
mW
Single 3.5 mA LVDS output at 983.04 MHz
7 mA
43
50
mW
Single 7 mA LVDS output at 122.88 MHz
141
164
mW
Single 7 mA LVDS output at 983.04 MHz
LVPECL Mode
46
51
mW
Single LVPECL output at 122.88 MHz
144
159
mW
Single LVPECL output at 983.04 MHz
HSTL Mode
8 mA
44
51
mW
Single 8 mA HSTL output at 122.88 MHz
143
165
mW
Single 8 mA HSTL output at 983.04 MHz
16 mA
48
55
mW
Single 16 mA HSTL output at 122.88 MHz
153
176
mW
Single 16 mA HSTL output at 983.04 MHz
CMOS Mode
6.6
7.9
mW
Single 3.3 V CMOS output at 15.36 MHz
9.9
11.9
mW
Dual complementary 3.3 V CMOS output at 15.36 MHz
9.9
11.9
mW
Dual in-phase 3.3 V CMOS output at 15.36 MHz
Output Distribution, Driver On
Lower power mode on, (Channel x control register, Bit 4 = 1)
LVDS Mode
3.5 mA
28.5
33.6
mW
Single 3.5 mA LVDS output at 122.88 MHz
88
105.6
mW
Single 3.5 mA LVDS output at 983.04 MHz
7 mA
37
42.9
mW
Single 7 mA LVDS output at 122.88 MHz
98
113.7
mW
Single 7 mA LVDS output at 983.04 MHz
LVPECL Mode
40.5
46
mW
Single LVPECL output at 122.88 MHz
100
110
mW
Single LVPECL output at 983.04 MHz
HSTL Mode
8 mA
34
39.1
mW
Single 8 mA HSTL output at 122.88 MHz
94
108.1
mW
Single 8 mA HSTL output at 983.04 MHz
16 mA
48
55.2
mW
Single 16 mA HSTL output at 122.88 MHz
153
176
mW
Single 16 mA HSTL output at 983.04 MHz
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