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參數(shù)資料
| 型號： | AD9522-4BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 80/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 1.6GHZ VCO 64LFCSP |
| 標準包裝： | 750 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD9522-4
Rev. 0 | Page 81 of 84
A recommended termination circuit for the LVDS outputs is
shown in Figure 71. If ac coupling is necessary, place decoupling
capacitors either before or after the 100 Ω termination resistor.
VS
LVDS
VS
LVDS
100
DIFFERENTIAL (COUPLES)
07
225
-04
7
Figure 71. LVDS Output Termination
See the AN-586 Application Note at www.analog.com for more
information on LVDS.
CMOS CLOCK DISTRIBUTION
The output drivers of the AD9522 can be configured as CMOS
drivers. When selected as a CMOS driver, each output becomes
a pair of CMOS outputs, each of which can be individually
turned on or off and set as inverting or noninverting. These
outputs are 3.3 V CMOS compatible.
When single-ended CMOS clocking is used, some of the
following guidelines apply.
Point-to-point connections should be designed such that each
driver has only one receiver, if possible. Connecting outputs in
this manner allows for simple termination schemes and minimizes
ringing due to possible mismatched impedances on the output
trace. Series termination at the source is generally required to
provide transmission line matching and/or to reduce current
transients at the driver.
The value of the resistor is dependent on the board design and
timing requirements (typically 10 Ω to 100 Ω is used). CMOS
outputs are also limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
3 inches are recommended to preserve signal rise/fall times and
signal integrity.
CMOS
10
60.4
(1.0 INCH)
MICROSTRIP
07
22
5-
07
6
Figure 72. Series Termination of CMOS Output
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9522 do not supply enough current
to provide a full voltage swing with a low impedance resistive, far-
end termination, as shown in Figure 73. The far-end termination
network should match the PCB trace impedance and provide the
desired switching point. The reduced signal swing may still meet
receiver input requirements in some applications. This can be
useful when driving long trace lengths on less critical nets.
CMOS
10
50
100
VS
0
72
25
-0
77
Figure 73. CMOS Output with Far-End Termination
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9522 offers LVDS outputs that
are better suited for driving long traces where the inherent noise
immunity of differential signaling provides superior
performance for clocking converters.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9522-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVDS/24 CMOS Output Clock Generator |
| AD9522-5/PCBZ | 功能描述:BOARD EVALUATION FOR AD9522-5 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9522-5BCPZ | 功能描述:IC CLOCK GEN 2.4GHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9522-5BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2.4GHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9523 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs |
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