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參數(shù)資料
| 型號： | AD9520-4BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 71/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 1.6GHZ VCO 64LFCSP |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9520-4/PCBZ-ND - BOARD EVAL FOR AD9520-4 |
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Data Sheet
AD9520-4
Rev. A | Page 73 of 80
Reg.
Addr.
(Hex) Bits
Name
Description
0x195 [7:3]
Unused
Unused.
2
Channel 1 power-down
Channel 1 powers down.
0: normal operation (default).
1: powered down. (Setting this bit puts OUT3/OUT3, OUT4/OUT4, and OUT5/OUT5 into safe power-
down mode.)
1
Channel 1 direct to output
Connects OUT3, OUT4, and OUT5 to Divider 1 or directly to VCO or CLK.
0: OUT3, OUT4, and OUT5 are connected to Divider 1 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT3, OUT4, and OUT5.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT3, OUT4, and OUT5.
If Register 0x1E1[1:0] = 01b, there is no effect.
0
Disable Divider 1 DCC
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x196 [7:4]
Divider 2 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays low.
A value of 0x1 means that the divider is low for two input clock cycles (default: 0x1).
[3:0]
Divider 2 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays high.
A value of 0x1 means that the divider is high for two input clock cycles (default: 0x1).
0x197 7
Divider 2 bypass
Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
6
Divider 2 ignore SYNC
Ignores SYNC.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5
Divider 2 force high
Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that this bit
has no effect if the channel divider is bypassed, but the driver polarity can still be reversed.
0: divider output is forced to low (default).
1: divider output is forced to the setting stored in Bit 4 of this register.
4
Divider 2 start high
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0]
Divider 2 phase offset
Phase offset (default: 0x0).
0x198 [7:3]
Unused
Unused.
2
Channel 2 power-down
Channel 2 powers down.
0: normal operation (default).
1: powered down. (Setting this bit puts OUT6/OUT6, OUT7/OUT7, and OUT8/OUT8 into safe power-
down mode.)
1
Channel 2 direct to output
Connects OUT6, OUT7, and OUT8 to Divider 2 or directly to VCO or CLK.
0: OUT6, OUT7, and OUT8 are connected to Divider 2 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT6, OUT7, and OUT8.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT6, OUT7, and OUT8.
If Register 0x1E1[1:0] = 01b, there is no effect.
0
Disable Divider 2 DCC
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x199 [7:4]
Divider 3 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default: 0x0).
[3:0]
Divider 3 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default: 0x0).
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PDF描述 |
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| AD9520-5BCPZ-REEL7 | IC CLOCK GEN EXT VCO 64LFCSP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9520-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator |
| AD9520-5/PCBZ | 功能描述:BOARD EVAL FOR AD9520-5 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9520-5BCPZ | 功能描述:IC CLOCK GEN EXT VCO 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9520-5BCPZ-REEL7 | 功能描述:IC CLOCK GEN EXT VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9521JH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
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