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參數(shù)資料
| 型號： | AD9520-4BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 1.6GHZ VCO 64LFCSP |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標準包裝： | 750 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9520-4/PCBZ-ND - BOARD EVAL FOR AD9520-4 |
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Data Sheet
AD9520-4
Rev. A | Page 3 of 80
REVISION HISTORY
8/13—Rev. 0 to Rev. A
Changes to Features Section, Applications Section, and
General Description Section............................................................1
Changes to Table 2 ............................................................................4
Changes to Input Frequency Parameter and Input Sensitivity,
Differential Parameter Test Conditions/Comments, Table 3......7
Change to Output Differential Voltage, VOD Parameter Test
Conditions/Comments; Added Source Current and Sink
Current Parameters, Table 4 ............................................................7
Change to Output Skew, LVPECL Outputs Parameter Test
Conditions/Comments, Table 5 ......................................................8
Reordered Figure 2 to Figure 4........................................................9
Change to Reset Timing, Pulse Width Low Parameter, Table 15...15
Change to Maximum Power, Full Operation Parameter,
Internal VCO Value in Test Conditions/Comments, Table 18.... 16
Change to Junction Temperature, Table 19; Reformatted
Table 19.............................................................................................17
Changes to Table 21 ........................................................................18
Deleted Figure 13, Renumbered Sequentially .............................22
Reordered Figure 31 and Figure 32; Added Figure 33,
Renumbered Sequentially ..............................................................25
Change to Mode 0—Internal VCO and Clock Distribution
Section ..............................................................................................28
Change to Configuration of the PLL Section; Changes
to Charge Pump (CP) Section .......................................................34
Changes to On-Chip VCO Section and PLL External Loop
Filter Section; Added Figure 40, Figure 41, and Figure 42;
Changes to PLL Reference Inputs Section ...................................35
Changes to Reference Switchover Section ...................................36
Change to Prescaler Section; Changes to A and B Counters
Section, Changes to Table 29 .........................................................37
Changes to Current Source Digital Lock Detect (CSDLD)
Section ..............................................................................................38
Changes to Holdover Mode Section.............................................39
Changes to Frequency Status Monitors Section and VCO
Calibration Section .........................................................................41
Added Table 31, Renumbered Sequentially; Change to
Internal Zero Delay Mode Section................................................42
Changes to External Zero Delay Mode Section ..........................43
Change to Clock Frequency Division Section and VCO
Divider Section; Added Channel Divider Maximum
Frequency Section...........................................................................45
Reformatted Table 36 to Table 39..................................................46
Change to Phase Offset or Coarse Time Delay Section.............47
Change to LVPECL Output Drivers Section; Changes to
CMOS Output Drivers Section; Change to Power-On Reset
Section ..............................................................................................49
Changes to Soft Reset via the Serial Port Section and Soft
Reset to Settings in EEPROM When EEPROM Pin = 0b
via the Serial Port Section ..............................................................50
Change to Pin Descriptions Section, SPI Mode Operation
Section, and Write Section.............................................................54
Changes to SPI Instruction Word (16 Bits) Section ...................55
Changes to EEPROM Operations Section, Writing to the
EEPROM Section, and Reading from the EEPROM Section ...58
Changes to Programming the EEPROM Buffer Segment
Section, Register Section Definition Group Section; Added
Operational Codes Section Heading............................................59
Changes to Table 50 ........................................................................61
Added Unused Bits to Register Map Descriptions Section;
Changes to Address 0x000, Bit 5, and Added Address 0x003,
Table 51; Changes to Address 0x000, Bit 5, and Added
Address 0x003, Table 52.................................................................64
Changes to Address 0x017, Bits[7:2], Table 54............................66
Changes to Address 0x018, Bit 4 and Bits[2:1], Table 54...........67
Changes to Address 0x01B, Bits[4:0], Setting 01101, Table 54 ....69
Changes to Address 0x191, Bit 5, and Address 0x194, Bit 5,
Table 56.............................................................................................72
Changes to Address 0x197, Bit 5, Table 56 ..................................73
Changes to Address 0x19A, Bit 5, Table 56 .................................74
Changes to Table 60 ........................................................................75
Changes to Address 0xB02, Bit 0, and Address 0xB03, Bit 0,
Table 61.............................................................................................76
Change to Frequency Planning Using the AD9520 Section .....77
Added LVPECL Y-Termination and Far-End Thevenin
Termination Headings; Change to LVPECL Y-Termination
Section; Changes to CMOS Clock Distribution Section ...........78
8/08—Revision 0: Initial Version
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9520-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator |
| AD9520-5/PCBZ | 功能描述:BOARD EVAL FOR AD9520-5 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9520-5BCPZ | 功能描述:IC CLOCK GEN EXT VCO 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9520-5BCPZ-REEL7 | 功能描述:IC CLOCK GEN EXT VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9521JH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
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