- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16534 > AD9518-4A/PCBZ (Analog Devices Inc)BOARD EVALUATION FOR AD9518-4A PDF資料下載
參數(shù)資料
| 型號： | AD9518-4A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9518-4A |
| 設(shè)計資源： | AD9518 Schematics AD9518 Gerber Files AD9518-4 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9518-4A |
| 主要屬性： | 2 輸入，14 輸出，1.6GHz VCO |
| 次要屬性： | LVPECL 輸出邏輯 |
| 已供物品： | 板 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
Data Sheet
AD9518-4
Rev. B | Page 37 of 64
Synchronizing the Outputs—Sync Function
The most common way to execute the sync function is to use
the SYNC pin to do a manual synchronization of the outputs.
This requires a low-going signal on the SYNC pin, which is held
low and then released when synchronization is desired. The
timing of the sync operation is shown in
(using the
VCO divider) and
(VCO divider not used). There is
an uncertainty of up to one cycle of the clock at the input to the
channel divider due to the asynchronous nature of the SYNC
signal with respect to the clock edges inside the
. The
delay from the
SYNC rising edge to the beginning of synchronized
output clocking is between 14 and 15 cycles of clock at the channel
divider input, plus either one cycle of the VCO divider input
(see
), or one cycle of the channel divider input (see
), depending on whether the VCO divider is used.
Cycles are counted from the rising edge of the signal.
The AD9518 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions and subsequently releasing these
outputs to continue clocking at the same instant with the preset
conditions applied. This allows for the alignment of the edges of
two or more outputs or for the spacing of edges according to the
coarse phase offset settings for two or more outputs.
Output synchronization is executed in several ways, as follows:
By forcing the SYNC pin low, then releasing it (manual sync).
By setting, then resetting, any one of the following three bits:
the soft sync bit (Register 0x230[0]), the soft reset bit
(Register 0x000[2] [mirrored]), and the power-down
distribution reference bit (Register 0x230[1]).
Another common way to execute the sync function is by setting
and resetting the soft sync bit at Register 0x230[0] (see Table 43
through Table 49 for details). Both the setting and resetting
of the soft sync bit require an update all registers operation
(Register 0x232[0] = 1) to take effect.
By executing synchronization of the outputs as part of the
chip power-up sequence.
By forcing the RESET pin low, then releasing it (chip reset).
By forcing the PD pin low, then releasing (chip power-down).
Following completion of a VCO calibration. An internal
SYNC signal is automatically asserted at the beginning of
a VCO calibration, then released upon its completion.
1
2
34
56
7
8
910
INPUT TO VCO DIVIDER
INPUT TO CHANNEL DIVIDER
OUTPUT OF
CHANNEL DIVIDER
SYNC PIN
1
11
12
13
14
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
06
433
-0
73
Figure 41. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input
INPUT TO CLK
IINPUT TO CHANNEL DIVIDER
OUTPUT OF
CHANNEL DIVIDER
SYNC PIN
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
12
3
4
5
6
7
8
910
11
12
13
14
1
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
0
643
3-
07
4
Figure 42. SYNC Timing When VCO Divider Is Not Used—CLK Input Only
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BA6920FP-Y | IC DRIVER REVERSE MOTOR HSOP25 |
| VE-JTW-EZ-S | CONVERTER MOD DC/DC 5.5V 25W |
| AD9518-2A/PCBZ | BOARD EVALUATION FOR AD9518-2A |
| FCBP110LD1L10 | CABLE 10.5GBPS 10M LASERWIRE |
| ADCLK946/PCBZ | KIT EVAL CLK BUFF ADCLK946 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9518-4BCPZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9518-4BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9520 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers |
| AD9520-0 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO |
| AD9520-0/PCBZ | 功能描述:BOARD EVAL AD9520-0 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。