參數(shù)資料
型號(hào)： AD9518-2ABCPZ-RL7
廠商： Analog Devices Inc
文件頁數(shù)： 7/64頁
文件大?。?/td> 0K
描述： IC CLOCK GEN 6CH 2.2GHZ 48LFCSP
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:6
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.33GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
Data Sheet
AD9518-2
Rev. C | Page 15 of 64
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
13
I
3.3 V CMOS
SCLK
Serial Control Port Data Clock Signal.
14
I
3.3 V CMOS
CS
Serial Control Port Chip Select, Active Low. This pin has an internal 30 k pull-up
resistor.
15
O
3.3 V CMOS
SDO
Serial Control Port. Unidirectional serial data output.
16
I/O
3.3 V CMOS
SDIO
Serial Control Port. Bidirectional serial data input/output.
17
I
3.3 V CMOS
RESET
Chip Reset, Active Low. This pin has an internal 30 k pull-up resistor.
18
I
3.3 V CMOS
PD
Chip Power Down, Active Low. This pin has an internal 30 k pull-up resistor.
19
O
LVPECL
OUT4
LVPECL Output; One Side of a Differential LVPECL Output.
20
O
LVPECL
OUT4
LVPECL Output; One Side of a Differential LVPECL Output.
21, 30, 31,
40
I
Power
VS_LVPECL
Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.
22
O
LVPECL
OUT5
LVPECL Output; One Side of a Differential LVPECL Output.
23
O
LVPECL
OUT5
LVPECL Output; One Side of a Differential LVPECL Output.
27, 34
GND
Ground. See the description for EPAD.
28
O
LVPECL
OUT3
LVPECL Output; One Side of a Differential LVPECL Output.
29
O
LVPECL
OUT3
LVPECL Output; One Side of a Differential LVPECL Output.
32
O
LVPECL
OUT2
LVPECL Output; One Side of a Differential LVPECL Output.
33
O
LVPECL
OUT2
LVPECL Output; One Side of a Differential LVPECL Output.
36
NC
No Connection.
38
O
LVPECL
OUT1
LVPECL Output; One Side of a Differential LVPECL Output.
39
O
LVPECL
OUT1
LVPECL Output; One Side of a Differential LVPECL Output.
41
O
LVPECL
OUT0
LVPECL Output; One Side of a Differential LVPECL Output.
42
O
LVPECL
OUT0
LVPECL Output; One Side of a Differential LVPECL Output.
44
O
Current set
resistor
RSET
Resistor connected here sets internal bias currents. Nominal value = 4.12 k.
46
O
Current set
resistor
CPRSET
Resistor connected here sets the CP current range. Nominal value = 5.1 k.
47
I
Reference
input
REFIN (REF2)
Along with REFIN, this is the self-biased differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF2.
48
I
Reference
input
REFIN (REF1)
Along with REFIN, this is the self-biased differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF1.
EPAD
GND
Ground. The external paddle on the bottom of the package must be connected to
ground for proper operation.
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