參數(shù)資料
型號(hào)： AD9517-2ABCPZ-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 39/80頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN 2.2GHZ VCO 48LFCSP
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:12
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.33GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
AD9517-2
Data Sheet
Rev. E | Page 44 of 80
Phase Offset or Coarse Time Delay (0, 1)
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 38).
These settings determine the number of cycles (successive
rising edges) of the channel divider input frequency by which to
offset, or delay, the rising edge of the output of the divider. This
delay is with respect to a nondelayed output (that is, with a
phase offset of zero). The amount of the delay is set by five bits
loaded into the phase offset (PO) register plus the start high (SH)
bit for each channel divider. When the start high bit is set, the
delay is also affected by the number of low cycles (M) that are
programmed for the divider.
The sync function must be used to make phase offsets effective
Table 38. Setting Phase Offset and Division for Divider 0 and
Divider 1
Divider
Start
High (SH)
Phase
Offset (PO)
Low Cycles
M
High Cycles
N
0
0x191[4]
0x191[3:0]
0x190[7:4]
0x190[3:0]
1
0x197[4]
0x197[3:0]
0x196[7:4]
0x196[3:0]
Let
Δt = delay (in seconds).
Δc = delay (in cycles of clock signal at input to DX).
TX = period of the clock signal at the input of the divider, DX
(in seconds).
Φ = 16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]
The channel divide-by is set as N = high cycles and M = low cycles.
Case 1
For Φ ≤ 15:
Δt = Φ × TX
Δc = Δt/TX = Φ
Case 2
For Φ ≥ 16:
Δt = (Φ 16 + M + 1) × TX
Δc = Δt/TX
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 55 shows the results of setting such a coarse
offset between outputs.
CHANNEL DIVIDER OUTPUTS
DIV = 4, DUTY = 50%
0
123
4567
89 10 11 12 13 14 15
Tx
DIVIDER 0
DIVIDER 1
DIVIDER 2
CHANNEL
DIVIDER INPUT
SH = 0
PO = 0
SH = 0
PO = 1
SH = 0
PO = 2
1 × Tx
2 × Tx
06
42
6-
0
71
Figure 55. Effect of Coarse Phase Offset (or Delay)
Channel Dividers—LVDS/CMOS Outputs
Channel Divider 2 and Channel Divider 3 each drive a pair of
LVDS outputs, giving a total of four LVDS outputs (OUT4 to
OUT7). Alternatively, each of these LVDS differential outputs
can be configured individually as a pair (A and B) of CMOS
single-ended outputs, providing for up to eight CMOS outputs.
By default, the B output of each pair is off but can be turned on
as desired.
Channel Divider 2 and Channel Divider 3 each consist of two
cascaded, 2 to 32, frequency dividers. The channel frequency
division is DX.1 × DX.2 or up to 1024. Divide-by-1 is achieved by
bypassing one or both of these dividers. Both of the dividers
also have DCC enabled by default, but this function can be
disabled, if desired, by setting the DCCOFF bit of the channel.
A coarse phase offset or delay is also programmable (see the
section). The channel dividers operate up to 1600 MHz. The
features and settings of the dividers are selected by programming
the appropriate setup and control registers (see Table 52 and
Table 39. Setting Division (DX) for Divider 2, Divider 31
Divider
M
N
Bypass
DCCOFF
2
2.1
0x199[7:4]
0x199[3:0]
0x19C[4]
0x19D[0]
2.2
0x19B[7:4]
0x19B[3:0]
0x19C[5]
0x19D[0]
3
3.1
0x19E[7:4]
0x19E[3:0]
0x1A1[4]
0x1A2[0]
3.2
0x1A0[7:4]
0x1A0[3:0]
0x1A1[5]
0x1A2[0]
1 Note that the value stored in the register = # of cycles minus 1.
Channel Frequency Division (Divider 2 and Divider 3)
The division for each channel divider is set by the bits in the
registers for the individual dividers (X.Y = 2.1, 2.2, 3.1, and 3.2)
Number of Low Cycles = MX.Y + 1
Number of High Cycles = NX.Y + 1
When both X.1 and X.2 are bypassed, DX = 1 × 1 = 1.
When only X.2 is bypassed, DX = (NX.1 + MX.1 + 2) × 1.
When both X.1 and X.2 are not bypassed, DX = (NX.1 + MX.1 + 2) ×
(NX.2 + MX.2 + 2).
By cascading the dividers, channel division up to 1024 can be
obtained. However, not all integer value divisions from 1 to
1024 are obtainable; only the values that are the product of the
separate divisions of the two dividers (DX.1 × DX.2) can be realized.
If only one divider is needed when using Divider 2 and Divider 3,
use the first one (X.1) and bypass the second one (X.2). Do not
bypass X.1 and use X.2.
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