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參數(shù)資料
| 型號： | AD9517-2ABCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/80頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.2GHZ VCO 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:12 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.33GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
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AD9517-2
Data Sheet
Rev. E | Page 18 of 80
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13
14
15
16
17
18
19
20
21
22
23
24
S
CL
K
CS
S
DO
S
DI
O
R
ESET
PD
OU
T2
OU
T2
VS_
L
VPEC
L
OU
T3
OU
T3
VS
48
47
46
45
44
43
42
41
40
39
38
37
RE
F
IN
(
RE
F
1)
RE
F
IN
(
RE
F
2)
C
PR
SET
VS
R
SET
VS
OU
T0
OU
T0
VS_
L
VPEC
L
OU
T1
OU
T1
VS
1
2
3
4
5
6
7
8
9
10
11
12
35
36
34
33
32
31
30
29
28
27
26
25
AD9517-2
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
CP
STATUS
CLK
VCP
REFMON
LD
BYPASS
VS
REF_SEL
LF
SYNC
CLK
OUT7 (OUT7A)
OUT5 (OUT5A)
OUT6 (OUT6A)
OUT4 (OUT4A)
VS
OUT6 (OUT6B)
OUT7 (OUT7B)
OUT5 (OUT5B)
OUT4 (OUT4B)
06426-
003
NOTES
1. THE EXTERNAL PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 6. Pin Configuration
Table 20. Pin Function Descriptions
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
1
I
3.3 V CMOS
REFMON
Reference Monitor (Output). This pin has multiple selectable outputs; see Table 54,
Register 0x01B.
2
O
3.3 V CMOS
LD
Lock Detect (Output). This pin has multiple selectable outputs; see Table 54,
Register 0x01A.
3
I
Power
VCP
Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.0 V. This pin is usually 3.3 V for
most applications; but if a 5 V external VCXO is used, this pin should be 5 V.
4
O
3.3 V CMOS
CP
Charge Pump (Output). Connects to external loop filter.
5
O
3.3 V CMOS
STATUS
Status (Output). This pin has multiple selectable outputs; see Table 54, Register 0x017.
6
I
3.3 V CMOS
REF_SEL
Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 k
pull-down resistor.
7
I
3.3 V CMOS
SYNC
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is also used for manual holdover. Active low. This pin has an
internal 30 k pull-up resistor.
8
I
Loop filter
LF
Loop Filter (Input). Connects to VCO control voltage node internally. This pin has
31 pF of internal capacitance to ground, which may influence the loop filter design
for large loop bandwidths.
9
O
Loop filter
BYPASS
This pin is for bypassing the LDO to ground with a capacitor.
10, 24, 25,
30, 31, 36,
37, 43, 45
I
Power
VS
3.3 V Power Pins.
11
I
Differential
clock input
CLK
Along with CLK, this is the self-biased differential input for the clock distribution
section. This pin can be left floating if internal VCO is used.
12
I
Differential
clock input
CLK
Along with CLK, this is the self-biased differential input for the clock distribution
section. This pin can be left floating if internal VCO is used.
13
I
3.3 V CMOS
SCLK
Serial Control Port Data Clock Signal.
14
I
3.3 V CMOS
CS
Serial Control Port Chip Select; Active Low. This pin has an internal 30 k pull-up
resistor.
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