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參數(shù)資料
| 型號(hào)： | AD9516-3BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 73/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK PLL/VCO 2GHZ 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:14 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.25GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9516-3/PCBZ-ND - BOARD EVAL FOR AD9516-3 2.0GHZ |
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Data Sheet
AD9516-3
Rev. C | Page 75 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x19C
5
Bypass Divider 3.2
Bypasses (and powers down) 3.2 divider logic, routes clock to 3.2 output.
0: does not bypass (default).
1: bypasses.
4
Bypass Divider 3.1
Bypasses (and powers down) 3.1 divider logic, routes clock to 3.1 output.
0: does not bypass 3.1 divider logic (default).
1: bypasses 3.1 divider logic.
3
Divider 3 nosync
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
2
Divider 3 force high
Force Divider 3 output high. Requires that nosync also be set.
0: forces low (default).
1: forces high.
1
Start High Divider 3.2
Divider 3.2 starts high/low.
0: starts low (default).
1: starts high.
0
Start High Divider 3.1
Divider 3.1 starts high/low.
0: starts low (default).
1: starts high.
0x19D
0
Divider 3 DCCOFF
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x19E
[7:4]
Low Cycles Divider 4.1
Number of clock cycles (minus 1) of 4.1 divider input during which 4.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0]
High Cycles Divider 4.1
Number of clock cycles (minus 1) of 4.1 divider input during which 4.1 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
0x19F
[7:4]
Phase Offset Divider 4.2
Refer to LVDS/CMOS channel divider function description (default = 0x0).
[3:0]
Phase Offset Divider 4.1
Refer to LVDS/CMOS channel divider function description (default = 0x0).
0x1A0
[7:4]
Low Cycles Divider 4.2
Number of clock cycles (minus 1) of 4.2 divider input during which 4.2 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0]
High Cycles Divider 4.2
Number of clock cycles (minus 1) of 4.2 divider input during which 4.2 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
0x1A1
5
Bypass Divider 4.2
Bypasses (and powers down) 4.2 divider logic; route clock to 4.2 output.
0: does not bypass 4.2 divider logic (default).
1: bypasses 4.2 divider logic.
4
Bypass Divider 4.1
Bypasses (and powers down) 4.1 divider logic; route clock to 4.1 output.
0: does not bypass 4.1 divider logic (default).
1: bypasses 4.1 divider logic.
3
Divider 4 nosync
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
2
Divider 4 force high
Forces Divider 4 output high. Requires that nosync also be set.
0: forces low (default).
1: forces high.
1
Start High Divider 4.2
Divider 4.2 starts high/low.
0: starts low (default).
1: starts high.
0
Start High Divider 4.1
Divider 4.1 starts high/low.
0: starts low (default).
1: starts high.
0x1A2
0
Divider 4 DCCOFF
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9516-4BCPZ-REEL7 | IC CLOCK GEN 1.8GHZ VCO 64-LFCSP |
| AD9516-5BCPZ | IC CLOCK GEN W/PLL 64-LFCSP |
| AD9517-0ABCPZ-RL7 | IC CLOCK GEN 2.8GHZ VCO 48LFCSP |
| AD9517-1ABCPZ-RL7 | IC CLOCK GEN 2.5GHZ VCO 48LFCSP |
| AD9517-2ABCPZ-RL7 | IC CLOCK GEN 2.2GHZ VCO 48LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9516-4 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Output Clock Generator with Integrated 1.6 GHz VCO |
| AD9516-4/PCBZ | 功能描述:BOARD EVAL FOR AD9516-4 1.8GHZ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9516-4/PCBZ | 制造商:Analog Devices 功能描述:AD9516-4, PLL CLOCK SYNTHESIZER, EVALUAT |
| AD9516-4BCPZ | 功能描述:IC CLOCK GEN 1.6GHZ VCO 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9516-4BCPZ | 制造商:Analog Devices 功能描述:CLOCK GENERATOR, 1.8GHZ, LFCSP-64 |
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