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參數(shù)資料
| 型號： | AD9516-3BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 42/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK PLL/VCO 2GHZ 64LFCSP |
| 標準包裝： | 750 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:14 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.25GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9516-3/PCBZ-ND - BOARD EVAL FOR AD9516-3 2.0GHZ |
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Data Sheet
AD9516-3
Rev. C | Page 47 of 80
12
3
4
5
6
7
8
910
INPUT TO VCO DIVIDER
INPUT TO CHANNEL DIVIDER
OUTPUT OF
CHANNEL DIVIDER
SYNC PIN
1
11
12
13
14
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
06
42
2-
0
73
Figure 57. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input
INPUT TO CLK
INPUT TO CHANNEL DIVIDER
OUTPUT OF
CHANNEL DIVIDER
SYNC PIN
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
12
3
4
5
6
7
8
910
11
12
13
14
1
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
0
6
422
-07
4
Figure 58. SYNC Timing When VCO Divider Is Not Used—CLK Input Only
A sync operation brings all outputs that have not been excluded
(by the nosync bit) to a preset condition before allowing the
outputs to begin clocking in synchronicity. The preset condition
takes into account the settings in each of the channel’s start high
bit and its phase offset. These settings govern both the static
state of each output when the SYNC operation is happening and
the state and relative phase of the outputs when they begin
clocking again upon completion of the SYNC operation.
Between outputs and after synchronization, this allows for the
setting of phase offsets.
The AD9516 outputs are in pairs, sharing a channel divider per
pair (two pairs of pairs, four outputs, in the case of CMOS). The
synchronization conditions apply to both outputs of a pair.
Each channel (a divider and its outputs) can be excluded from
any sync operation by setting the nosync bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a sync operation, and their
outputs are not synchronized with those of the nonexcluded
channels.
Clock Outputs
The AD9516 offers three different output level choices:
LVPECL, LVDS, and CMOS. OUT0 to OUT5 are LVPECL
differential outputs; and OUT6 to OUT9 are LVDS/CMOS
outputs. These outputs can be configured as either LVDS
differential or as pairs of single-ended CMOS outputs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9516-4BCPZ-REEL7 | IC CLOCK GEN 1.8GHZ VCO 64-LFCSP |
| AD9516-5BCPZ | IC CLOCK GEN W/PLL 64-LFCSP |
| AD9517-0ABCPZ-RL7 | IC CLOCK GEN 2.8GHZ VCO 48LFCSP |
| AD9517-1ABCPZ-RL7 | IC CLOCK GEN 2.5GHZ VCO 48LFCSP |
| AD9517-2ABCPZ-RL7 | IC CLOCK GEN 2.2GHZ VCO 48LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9516-4 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Output Clock Generator with Integrated 1.6 GHz VCO |
| AD9516-4/PCBZ | 功能描述:BOARD EVAL FOR AD9516-4 1.8GHZ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9516-4/PCBZ | 制造商:Analog Devices 功能描述:AD9516-4, PLL CLOCK SYNTHESIZER, EVALUAT |
| AD9516-4BCPZ | 功能描述:IC CLOCK GEN 1.6GHZ VCO 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9516-4BCPZ | 制造商:Analog Devices 功能描述:CLOCK GENERATOR, 1.8GHZ, LFCSP-64 |
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