參數(shù)資料
型號: AD9444BSVZ-80
廠商: Analog Devices Inc
文件頁數(shù): 37/40頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 80MSPS 100TQFP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.4W
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
輸入數(shù)目和類型: 1 個差分,單極
AD9444
Rev. 0 | Page 6 of 40
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
AD9444BSVZ-80
Parameter
Temp
Test Level
Min
Typ
Max
Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Full
VI
80
MSPS
Minimum Conversion Rate
Full
V
10
MSPS
CLK Period
Full
V
12.5
ns
CLK Pulse Width High1 (tCLKH)
Full
V
4
ns
CLK Pulse Width Low1 (tCLKL)
Full
V
4
ns
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (tPD)2 (DX, DCO+)
Full
IV
3
5.25
8
ns
Output Propagation Delay—LVDS (tPD)3 (DX+, DCO+)
Full
VI
3
5
7.5
ns
Pipeline Delay (Latency)
Full
V
12
Cycles
Aperture Delay (tA)
Full
V
ns
Aperture Uncertainty (Jitter, tJ)
Full
V
0.2
ps rms
1 With duty cycle stabilizer (DCS) enabled.
2 Output propagation delay is measured from clock 50% transition to data 50% transition, with 5 pF load.
3 LVDS RTERM = 100 . Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
N–12
N–11
N
N+1
AIN
CLK+
CLK–
DATA OUT
DCO+
DCO–
N
N+1
N–1
t
CLKH
t
CLKL
1/
fS
t
PD
12 CLOCK CYCLES
t
CPD
05089-002
Figure 2. LVDS Mode Timing Diagram
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