參數(shù)資料
型號(hào): AD9266BCPZ-20
廠商: Analog Devices Inc
文件頁數(shù): 30/32頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 20MSPS 32LFCSP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 16
采樣率(每秒): 20M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 63mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-WQ(5x5)
包裝: 托盤
輸入數(shù)目和類型: 2 個(gè)單端,單極;1 個(gè)差分,單極
Data Sheet
AD9266
Rev. A | Page 7 of 32
SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = 1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 4.
Parameter
Temp
AD9266-20/AD9266-40
AD9266-65
AD9266-80
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
CLOCK INPUT PARAMETERS
Input Clock Rate
Full
80/320
520
625
MHz
Conversion Rate1
Full
3
20/40
3
65
3
80
MSPS
CLK Period—Divide-by-1 Mode (tCLK)
Full
50/25
15.38
12.5
ns
CLK Pulse Width High (tCH)
25.0/12.5
7.69
6.25
ns
Aperture Delay (tA)
Full
1.0
ns
Aperture Uncertainty (Jitter, tJ)
Full
0.1
ps rms
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)
Full
1.84
3
3.90
1.84
3
3.90
1.84
3
3.90
ns
DCO Propagation Delay (tDCO)
Full
1.86
3
4.04
1.86
3
4.04
1.86
3
4.04
ns
DCO to Data Skew (tSKEW)
Full
0.53
0.1
0.72
0.53
0.1
0.72
0.53
0.1
0.72
ns
Pipeline Delay (Latency)
Full
9
Cycles
Wake-Up Time2
Full
350
s
Standby
Full
600/400
300
260
ns
OUT-OF-RANGE RECOVERY TIME
Full
2
Cycles
1
Conversion rate is the clock rate after the CLK divider.
2
Wake-up time is dependent on the value of the decoupling capacitors.
08678-
002
tCLK
tA
tDCO
tSKEW
tPD
VIN
CLK+
CLK–
DCO
D1_D0
N – 1
N
N + 1
N + 2
N + 3
N + 5
N + 6
N + 7
N + 8
D1N–9
D0N–9
D1N–8
D0N–8
D1N–7
D0N–7
D1N–6
D0N–6
D1N–5
D0N–5
D1N–4
D0N–4
D15N–9 D14N–9 D15N–8 D14N–8 D15N–7 D14N–7 D15N–6 D14N–6 D15N–5 D14N–5 D15N–4 D14N–4
D15_D14
Figure 2. CMOS Output Data Timing
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