1. NC = NO CONNECT." />
參數(shù)資料
型號(hào)： AD9266BCPZ-20
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/32頁(yè)
文件大小： 0K
描述： IC ADC 16BIT 20MSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 16
采樣率（每秒）： 20M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 63mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-WQ（5x5）
包裝： 托盤
輸入數(shù)目和類型： 2 個(gè)單端，單極；1 個(gè)差分，單極
AD9266
Data Sheet
Rev. A | Page 10 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE (PIN 0) IS THE ONLY GND
CONNECTION ON THE CHIP AND MUST BE CONNECTED
TO THE PCB AGND.
08678-
003
CLK+
CLK–
AVDD
CSB
SCLK/DFS
SDIO/PDWN
NC
AVDD
MODE/OR
DCO
(MSB) D15_D14
D13_D12
D11_D10
D9_D8
D7_D6
NC
D
R
V
DD
D1_D0
(
L
S
B)
D3_D2
D5_D4
A
V
DD
V
IN+
V
IN–
A
V
DD
RBI
AS
V
CM
SEN
SE
VR
EF
TOP VIEW
(Not to Scale)
AD9266
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
1
12
13
14
15
16
32
31
30
29
28
27
26
25
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
0, Exposed Paddle
AGND
The exposed paddle is the only ground connection on the chip. It must be soldered to the analog
ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength
benefits.
1, 2
CLK+, CLK
Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs.
3, 24, 29, 32
AVDD
1.8 V Supply Pin for ADC Core Domain.
4
CSB
SPI Chip Select. Active low enable, 30 k internal pull-up.
5
SCLK/DFS
SPI Clock Input in SPI Mode (SCLK). 30 k internal pull-down.
Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 k internal pull-down.
DFS high = twos complement output; DFS low = offset binary output.
6
SDIO/PDWN
SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 k internal pull-down.
Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 k internal pull-
down. See Table 14 for details.
7 to 12
NC
No Connect.
14 to 21
D1_D0 (LSB) to
(MSB) D15_D14
ADC Digital Outputs.
13
DRVDD
1.8 V to 3.3 V Supply Pin for Output Driver Domain.
22
DCO
Data Clock Digital Output.
23
MODE/OR
Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR).
Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1).
Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0).
Chip power-down (SPI Register 0x08, Bits[7:5] = 100b).
Chip standby (SPI Register 0x08, Bits[7:5] = 101b).
Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b).
Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b).
Out-of-range (OR) digital output only in non-SPI mode.
25
VREF
1.0 V Voltage Reference Input/Output. See Table 10.
26
SENSE
Reference Mode Selection. See Table 10.
27
VCM
Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.
28
RBIAS
Set Analog Current Bias. Connect to 10 k (1% tolerance) resistor to ground.
30, 31
VIN, VIN+
ADC Analog Inputs.
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