參數(shù)資料
型號(hào)： AD9266BCPZ-20
廠商： Analog Devices Inc
文件頁數(shù)： 21/32頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 20MSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 16
采樣率（每秒）： 20M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 63mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-WQ（5x5）
包裝： 托盤
輸入數(shù)目和類型： 2 個(gè)單端，單極；1 個(gè)差分，單極
AD9266
Data Sheet
Rev. A | Page 28 of 32
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 16 are not currently supported for this device.
Table 16.
Addr
(Hex)
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Comments
Chip Configuration Registers
0x00
SPI port
configuration
0
LSB
first
Soft
reset
1
Soft
reset
LSB first
0
0x18
The nibbles are
mirrored so that
LSB- or MSB-first
mode registers
correctly, regardless
of shift mode.
0x01
Chip ID
8-bit chip ID, Bits[7:0]
AD9266 = 0x78
Read
only
Unique chip ID
used to differentiate
devices; read only.
0x02
Chip grade
Open
Speed grade ID, Bits[6:4] (identify
device variants of chip ID)
20 MSPS = 000
40 MSPS = 001
65 MSPS = 010
80 MSPS = 011
Open
Read
only
Unique speed
grade ID used
to differentiate
devices; read only.
Device Index and Transfer Register
0xFF
Transfer
Open
Transfer
0x00
Synchronously
transfers data from
the master shift
register to the slave.
Program Registers
0x08
Modes
External
Pin 23 mode
input enable
External Pin 23
function when high
00 = full power-
down
01 = standby
10 = normal mode:
output disabled
11 = normal mode:
output enabled
Open
00 = chip run
01 = full power-down
10 = standby
11 = chip wide digital
reset
0x00
Determines various
generic modes of
chip operation.
0x09
Clock
Open
Duty cycle
stabilize
0x01
Enable internal
duty cycle stabilizer
(DCS).
0x0B
Clock divide
Open
Clock divider, Bits[2:0]
Clock divide ratio:
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x00
The divide ratio is
the value plus 1.
0x0D
Test mode
User test mode
00 = single
01 = alternate
10 = single once
11 = alternate once
Reset PN
long gen
Reset PN
short gen
Output test mode, Bits[3:0] (local)
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = 1/0 word toggle
1000 = user input
1001 = 1/0 bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
0x00
When set, the test
data is placed on
the output pins in
place of normal data.
0x10
Offset adjust
8-bit device offset adjustment, Bits[7:0] (local)
Offset adjust in LSBs from +127 to 128 (twos complement format)
0x00
Device offset trim.
0x14
Output mode
00 = 3.3 V CMOS
10 = 1.8 V CMOS
Open
Output
disable
Open
Output
invert
00 = offset binary
01 = twos complement
10 = gray code
11 = offset binary
0x00
Configures the
outputs and the
format of the data.
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