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參數(shù)資料
| 型號： | AD9260ASZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 2.5MHZ 44MQFP |
| 標(biāo)準包裝： | 800 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 585mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
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AD9260
Rev. C | Page 35 of 44
the AD9260 is referenced DVDD while the output drivers are
referenced to DRVDD. Also note that the SNR performance
of the AD9260 remains independent of the digital or driver
supply setting.
The decoupling shown in Figure 75, a 0.1 F ceramic chip
capacitor, is appropriate for a reasonable capacitive load on the
digital outputs (typically 20 pF on each pin). Applications
involving greater digital loads should consider increasing the
digital decoupling proportionally, and/or using external
buffers/latches.
0.1
F
0.1
F
DVDD
DVSS
AD9260
DRVDD
DRVSS
3
1
6
5
00581-C-075
Figure 75. Digital Supply Decoupling
A complete decoupling scheme will also include large tantalum
or electrolytic capacitors on the PCB to reduce low frequency
ripple to negligible levels. Refer to the AD9260/EB schematic
and layouts in Figure 80 to Figure 84 for more information
regarding the placement of decoupling capacitors.
An alternative layout and decoupling scheme is shown in Figure
76. This layout and decoupling scheme is well suited for
applications in which multiple AD9260s are located on the
same PC board and/or the AD9260 is part of a multicard
mixed-signal system in which grounds are tied back at the
system supplies (i.e., star ground configuration). In this case,
the AD9260 is treated as an analog component in which its
analog (i.e., AVDD) and digital (DVDD and DRVDD) supplies
are derived from the systems +5 V analog supply and all of the
AD9260’s ground pins are tied directly to the analog ground
plane which resides directly underneath the IC.
Referring to Figure 76, each supply pin is directly decoupled to
their respective ground pin or analog ground plane via a
ceramic 0.1 F chip capacitor. Surface mount ferrite beads are
used to isolate the analog (AVDD), digital (DVDD), and driver
supplies (DRVDD) of the AD9260 from the +5 V power bus.
Properly selected ferrite beads can provide more than 40 dB of
isolation from high frequency switching transients originating
from AD9260 supply pins. Further noise immunity from noise
is provided by the inherent power supply rejection of the
AD9260 as shown in Figure 70. If digital operation at 3 V is
desirable for power savings and or to provide for a 3 V digital
logic interface, a 5 V to 3 V linear regulator can be used to drive
DVDD and/or DRVDD. A more complete discussion on this
layout and decoupling scheme can be found in Chapter 7, pages
7-27 to 7-55 of the High speed Design Techniques seminar
book, which is available at:
FERRITE
BEAD CORE*
VA
SAMPLING CLOCK
GENERATOR
AD9260
0.1
F
0.1
F
10
F
0.1
F
0.1
F
0.1
F
DVDD
DVSS
AVDD
AVSS
AVDD
AVSS
AVDD
AVSS
DRVDD
DRVSS
CLK
BUFFER
LATCH
BITS 1–16,
DAV
VA
INSERT 5/3 VOLT LINEAR REGULATOR
FOR 3 OR 3.3V DIGITAL OPERATION
00581-C-076
Figure 76. High Frequency Supply Rejection
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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| AD9260-EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9260 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9260 - Bulk |
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