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| 型號： | AD9260ASZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 2.5MHZ 44MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 585mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
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AD9260
Rev. C | Page 31 of 44
applications in which the input of the A/D converters sees an
abrupt change, the data in the analog modulator and digital
filter will be corrupted.
For this reason, following a pulse on the RESET pin, or change
in channels (i.e., multiplexed applications only), the decimation
filters must be flushed of their data. These filters have a
memory length, hence delay, equal to the number of filter taps
times the clock rate of the converter. This memory length may
be interpreted in terms of a number of samples stored in the
decimation filter. For example, if the part is in 8× decimation
mode, the delay is 321/fCLOCK. This corresponds to 321 samples
stored in the decimation filter. These 321 samples must be
flushed from the AD9260 after RESET is pulsed high prior to
reusing the data from the AD9260. That is, the AD9260 should
be allowed to clock for 321 samples as the corrupted data is
flushed from the filters. If the part is in 4× or 2× decimation
mode, then the relatively smaller group delays of the 4× and 2×
decimation filters result fewer samples that must be flushed
from the filters (108 samples and 23 samples respectively).
In 2×, 4×, or 8× mode, RESET may be used to synchronize
multiple AD9260s clocked with the same clock. The decimation
filters in the AD9260 are clocked with an internal clock divider.
The state of this clock divider determines when the output data
becomes available (relative to CLK). In order to synchronize
multiple AD9260s clocked with the same clock, it is necessary
that the clock dividers in each of the individual AD9260s are all
reset to the same state. When RESET is asserted low, these clock
dividers are cleared. On the next falling edge of CLK following
the rising edge of RESET, the clock dividers begin counting and
the clock is applied to the digital decimation filters.
OTR Pin
The OTR pin is a synchronous output that is updated each CLK
period. It indicates that an overrange condition has occurred
within the AD9260. Ideally, OTR should be latched on the
falling edge of CLK to ensure proper setup-and-hold time.
However, since an overrange condition typically extends well
beyond one clock cycle (i.e., does not toggle at the CLK rate).
OTR typically remains high for more than a clock cycle,
allowing it to be successfully detected on the rising edge of CLK
or monitored asynchronously.
An overrange condition must be carefully handled because of
the group delays in the low-pass digital decimation filters in the
output stages of the AD9260. When the input signal exceeds the
full-scale range of the converter, this can have a variety of
effects upon the operation of the AD9260, depending on the
duration and amplitude of this overrange condition. A short
duration overrange condition (<< filter group delay) may cause
the analog modulator to briefly overrange without causing the
data in the low pass digital filters to exceed full scale. The
analog modulator is actually capable of processing signals
slightly (3%) beyond the full-scale range of the AD9260 without
internally clipping. A long duration overrange condition will
cause the digital filter data to exceed full scale. For this reason,
the OTR signal is generated using two separate internal out-of-
range detectors.
The first of these out-of-range detectors is placed at the output
of the analog modulator and indicates whether the modulator
output signal has extended 3% beyond the full-scale range of
the converter. If the modulator output signal exceeds 3%
beyond full scale, the digital data is hard-limited (i.e., clipped)
to a number that is 3% larger than full scale. Due to the delay of
the switched capacitor analog modulator, the OTR signal is
delayed 3 1/2 clock cycles relative to the clock edge in which the
overranged analog input signal was sampled.
The second out-of-range detector is placed at the output of the
stage three decimation filter and detects whether the low pass
filtered data has exceeded full scale. When this occurs, the filter
output data is hard limited to full scale. The OTR signal is a
logical OR function of the signals from these two internal out-
of-range detectors. If either of these detectors produces an out-
of-range signal, the OTR pin goes high and the data may be
seriously corrupted.
If the AD9260 is used in a system that incorporates automatic
gain control (AGC), the OTR signal may be used to indicate
that the signal amplitude should be reduced. This may be
particularly effective for use in maximizing the signal dynamic
range if the signal includes high-frequency components that
occasionally exceed full scale by a small amount. If, on the other
hand, the signal includes large amplitude low frequency
components that cause the digital filters to overrange, this may
cause the low pass digital filter to overrange. In this case the
data may become seriously corrupted and the digital filters may
need to be flushed. See the RESET pin function description
above for an explanation of the requirements for flushing the
digital filters.
OTR should be sampled with the falling edge of CLK. This
signal is invalid while CLK is HIGH.
MODE OPERATION
The Mode Select Pin (MODE) allows the user to select one of
four available digital filter modes using a single pin. Each mode
configures the internal decimation filter to decimate at: 1×, 2×,
4×, or 8×. Refer to Table 15 for mode pin ranges.
The mode selection is performed by using a set of internal
comparators, as illustrated in Figure 68, so that each mode
corresponds to a voltage range on the input of the MODE pin.
The output of the comparators are fed into encoding logic
where, on the falling edge of the clock, the encoded data
is latched.
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