- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1986 > AD9260ASZRL (Analog Devices Inc)IC ADC 16BIT 2.5MHZ 44MQFP PDF資料下載
參數(shù)資料
| 型號： | AD9260ASZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 2.5MHZ 44MQFP |
| 標準包裝： | 800 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 585mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
AD9260
Rev. C | Page 24 of 44
ANALOG INPUT AND REFERENCE OVERVIEW
Figure 60, a simplified model of the AD9260, highlights the
relationship between the analog inputs, VINA, VINB and the
reference voltage VREF. Like the voltage applied to the top of
the resistor ladder in a flash A/D converter, the value VREF
defines the maximum input voltage to the A/D converter. An
internal reference buffer in the AD9260 scales the reference
voltage VREF before it is applied internally to the AD9260 A/D
core. The scale factor of this reference buffer is 0.8.
Consequently, the maximum input voltage to the A/D core is
+0.8 × VREF. The minimum input voltage to the A/D core is
automatically defined to be –0.8 × VREF. With this scale factor,
the maximum differential input span of 4 V p-p is obtained
with a VREF voltage of 2.5 V. A smaller differential input span
may be obtained by using a VREF voltage of less than 2.5 V at
the expense of ac performance (refer to Figure 52).
A/D CORE
–0.8
× VREF
+0.8
× VREF
16
+
–
VINA
VINB
Σ
00581-C-060
Figure 60. Simplified Input Model
INPUT SPAN
The AD9260 is implemented with a differential input structure.
This structure allows the common-mode level (average voltage
of the two input pins) of the input signal to be varied
independently of the input span of the converter over a wide
range, as shown in Figure 50. Specifically, the input to the A/D
core is the difference of the voltages applied at the VINA and
VINB input pins. Therefore, the equation,
VINB
VINA
VCORE
=
(1)
defines the output of the differential input stage and provides
the input to the A/D core.
The voltage, VCORE, must satisfy the condition,
VREF
VCORE
VREF
×
+
≤
×
8
.
0
8
.
0
(2)
where VREF is the voltage at the VREF pin.
INPUT COMPLIANCE RANGE
In addition to the limitations on the differential span of the
input signal indicated in Equation 2, an additional limitation is
placed on the inputs by the analog input structure of the
AD9260. The analog input structure bounds the valid operating
range for VINA and VINB. The condition,
V
AVDD
VINB
V
AVSS
V
AVDD
VINA
V
AVSS
5
.
0
5
.
0
5
.
0
5
.
0
+
<
+
<
+
(3)
where AVSS is nominally 0 V and AVDD is nominally +5 V,
defines this requirement. Thus the valid inputs for VINA and
VINB are any combination that satisfies both Equations 2 and 3.
Note that the clock clamping method used in the differential
driver circuit shown in Figure 63 is sufficient for protecting the
AD9260 in an undervoltage condition.
For additional information showing the relationships between
VINA, VINB, VREF, and the digital output of the AD9260, see
Refer to Table 12 for a summary of the various analog input and
reference configurations.
ANALOG INPUT OPERATION
The analog input structure of the AD9260 is optimized to meet
the performance requirements for some of the most demanding
communication and data acquisition applications. This input
structure is composed of a switched-capacitor network that
samples the input signal applied to pins VINA and VINB on
every rising edge of the CLK pin. The input switched capacitors
are charged to the input voltage during each period of CLK. The
resulting charge, q, on these capacitors is equal to C × VIN,
where C is the input capacitor. The change in charge on these
capacitors, delta q, as the capacitors are charged from a previous
sample of the input signal to the next sample, is approximated
in the following equation,
(
)
2
~
×
=
×
N
V
C
deltaV
C
q
delta
(4)
where VN represents the present sample of the input signal and
VN–2 represents the sample taken two clock cycles earlier. The
average current flow into the input (provided from an external
source) is given in the following equation,
(
)
CLOCK
N
f
V
C
T
q
delta
I
×
×
=
2
~
/
(5)
where T represents the period of CLK and fCLOCK represents the
frequency of CLK. Equations 4 and 5 provide simplifying
approximations of the operation of the analog input structure of
the AD9260. A more exact, detailed description and analysis of
the input operation follows.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9262BCPZ-10 | IC ADC 16BIT 10MHZ 64LFCSP |
| AD9266BCPZRL7-20 | IC ADC 16BIT 20MSPS 32LFCSP |
| AD9269BCPZRL7-20 | IC ADC 16BIT 20MSPS DL 64LFCSP |
| AD9271BSVZ-40 | IC ADC OCT 12BIT 40MSPS 100-TQFP |
| AD9280ARSRL | IC ADC 8BIT CMOS 32MSPS 28-SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9260EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
| AD9260-EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9260 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9260 - Bulk |
| AD9261-10EBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 16Bit 10 MHz Sigma Delta ADC EB RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9261BCPZ-10 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16Bit 10 MHz Sigma Delta ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
| AD9261BCPZRL7-10 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16Bit 10 MHz Sigma Delta ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
發(fā)布緊急采購，3分鐘左右您將得到回復。