參數(shù)資料
型號(hào)： AD9257BCPZRL7-40
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/40頁(yè)
文件大小： 0K
描述： IC ADC 14BIT SRL 40MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 14
采樣率（每秒）： 40M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 8
功率耗散（最大）： 434mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)差分
Data Sheet
AD9257
Rev. A | Page 23 of 40
DIGITAL OUTPUTS AND TIMING
The AD9257 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option (similar to the IEEE 1596.3 standard) via the
SPI. The LVDS driver current is derived on chip and sets the
output current at each output equal to a nominal 3.5 mA. A 100
differential termination resistor placed at the LVDS receiver
inputs results in a nominal 350 mV swing (or 700 mV p-p
differential) at the receiver.
When operating in reduced range mode, the output current is
reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-p
differential) across a 100 termination at the receiver.
The AD9257 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 termination resistor
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is recom-
mended that the trace length be less than 24 inches and the
differential output traces be close together and at equal lengths.
An example of the FCO and data stream with proper trace
length and position is shown in Figure 57. An example of LVDS
output timing in reduced range mode is shown in Figure 58.
FCO 500mV/DIV
DCO 500mV/DIV
DATA 500mV/DIV
5ns/DIV
10206-
056
Figure 57. LVDS Output Timing Example in ANSI-644 Mode (Default)
FCO 500mV/DIV
DCO 500mV/DIV
DATA 500mV/DIV
5ns/DIV
10206-
057
Figure 58. LVDS Output Timing Example in Reduced Range Mode
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