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參數(shù)資料
| 型號： | AD9252ABCPZ-50 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/52頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SRL 50MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 50M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 功率耗散（最大）： | 773mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 16 個單端，單極；8 個差分，單極 |
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Data Sheet
AD9252
Rev. E | Page 19 of 52
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9252 sample clock inputs
(CLK+ and CLK) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK pins
via a transformer or capacitors. These pins are biased internally
and require no additional biasing.
Figure 40 shows the preferred method for clocking the AD9252.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9252 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9252, and it preserves the
fast rise and fall times of the signal, which are critical to low
jitter performance.
0.1F
SCHOTTKY
DIODES:
HSM2812
CLK+
50
100
CLK–
CLK+
ADC
AD9252
Mini-Circuits
ADT1-1WT, 1:1Z
XFMR
06296-
022
Figure 40. Transformer-Coupled Differential Clock
Another option is to ac-couple a differential PECL signal to the
sample clock input pins as shown in Figure 41. The AD9510/
drivers offers excellent jitter performance.
100
0.1F
240
240
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
50
1
50
1
CLK
150
RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9252
PECL DRIVER
06296-
023
CLK+
CLK–
Figure 41. Differential PECL Sample Clock
10
0
0.1F
501
LVDS DRIVER
501
CLK
1
50 RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9252
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
06296-
024
CLK+
CLK–
Figure 42. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 k resistor (see Figure 43). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V, making the
selection of the drive logic voltage very flexible.
0.1F
39k
CMOS DRIVER
50
1
OPTIONAL
100
0.1F
CLK
1
50 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9252
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
06296-
025
CLK+
Figure 43. Single-Ended 1.8 V CMOS Sample Clock
0.1F
CMOS DRIVER
50
1
OPTIONAL
100
CLK
150
RESISTOR IS OPTIONAL.
0.1F
CLK–
CLK+
ADC
AD9252
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
06296-
026
CLK+
Figure 44. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9252 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9252. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See the Memory Map section for
more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9252ABCPZ-50 | 制造商:Analog Devices 功能描述:IC, ADC, 14BIT, 50MSPS, LVDS, SERIAL |
| AD9252ABCPZRL7-50 | 功能描述:IC ADC 14BIT SRL 50MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9252BCPZ-50 | 制造商:Analog Devices 功能描述:IC ((NW)) 制造商:Analog Devices 功能描述:IC,A/D CONVERTER,OCTAL,14-BIT,LLCC,64PIN |
| AD9252BCPZRL7-50 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal, 14-Bit, 50 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9253 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS |
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