參數(shù)資料
型號： AD9239BCPZ-170
廠商： Analog Devices Inc
文件頁數(shù)： 17/40頁
文件大?。?/td> 0K
描述： IC ADC 12BIT DUAL 170MSPS 72PIN
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 1.22W
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP
包裝： 托盤
輸入數(shù)目和類型： 8 個單端，單極；4 個差分，單極
AD9239
Data Sheet
Rev. C | Page 24 of 40
–200
–100
0
100
200
–30
–10
0
10
30
–0.5
0.5
TIME (ps)
ULS
400
600
200
0
–200
–400
–600
V
OLTA
GE
(m
V)
HEIGHT1: EYE DIAGRAM
TIE1: HISTOGRAM
TJ@BERI: BATHTUB
1
+
500
600
400
300
200
100
0
H
ITS
0.0001
0.01
1
1E–6
1E–8
1E–10
1E–12
1E–14
BE
R
06980-
094
3
+
2
+
EYE: ALL BITS
OFFSET: 0.015
ULS: 5000: 40044, TOTAL: 12000: 80091
(y1)
(y2)
(Δy)
–375.023m
+409.847m
+784.671m
Figure 63. Digital Outputs Data Eye with Trace Lengths Less than 6 Inches on Standard FR-4, External 100 Terminations at Receiver
–200
–100
0
100
200
–50
0
50
TIME (ps)
400
600
200
0
–200
–400
–600
VO
LT
AG
E
(m
V)
250
300
200
150
100
50
0
H
ITS
HEIGHT1: EYE DIAGRAM
TIE1: HISTOGRAM
0
–0.5
0.5
ULS
0.0001
0.01
1
1E–6
1E–8
1E–10
1E–12
1E–14
BE
R
TJ@BERI: BATHTUB
06980-
095
3
+
2
+
1
+
(y1)
(y2)
(Δy)
–402.016m
+398.373m
+800.389m
EYE: ALL BITS
OFFSET: 0.015
ULS: 5000: 40044, TOTAL 8000: 40044
Figure 64. Digital Outputs Data Eye with Trace Lengths Greater than 12 Inches on Standard FR-4, External 100 Terminations at Receiver
An example of the digital output (default) data eye and a time
interval error (TIE) jitter histogram with trace lengths less than
6 inches on standard FR-4 material is shown in Figure 63.
Figure 64 shows an example of trace lengths exceeding 12 inches
on standard FR-4 material. Notice that the TIE jitter histogram
reflects the decrease of the data eye opening as the edge deviates
from the ideal position. It is the user’s responsibility to determine
if the waveforms meet the timing budget of the design when the
trace lengths exceed 6 inches.
Additional SPI options allow the user to further increase the
output driver voltage swing of all four outputs in order to drive
longer trace lengths (see Register 15 in Table 15). Even though
this produces sharper rise and fall times on the data edges and is
less prone to bit errors, the power dissipation of the DRVDD
supply increases when this option is used. See the Memory Map
section for more details.
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 9.
To change the output data format to twos complement or gray
code, see the Memory Map section.
Table 9. Digital Output Coding
Code
(VIN + x) (VIN x),
Input Span = 1.25 V p-p (V)
Digital Output Offset Binary
(D11 ... D0)
4095
+0.625
1111 1111 1111
2048
0.00
1000 0000 0000
2047
0.000305
0111 1111 1111
0
0.625
0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to N bits
times the sample clock rate, in addition to some amount of
overhead to account for the 8-bit header and error correction, for a
maximum of 3.36 Gbps (that is, 12 bits × 210 MSPS × 64/48 =
3.36 Gbps). The lowest typical clock rate is 100 MSPS. For clock
rates slower than 100 MSPS, refer to Register 21 in the SPI
Memory Map. This option allows the user to adjust the PLL
loop bandwidth in order to use clock rates as low as 50 MSPS.
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