參數(shù)資料
型號(hào)： AD9228ABCPZRL7-65
廠商： Analog Devices Inc
文件頁數(shù)： 19/56頁
文件大?。?/td> 0K
描述： IC ADC 12BIT SPI/SRL 65M 48LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 12
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 510mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極
AD9228
Data Sheet
Rev. E | Page 26 of 56
05
72
7
-04
3
100
50
0
–100ps
0ps
100ps
T
IE
J
IT
T
ER
HI
S
T
O
G
R
AM
(
H
it
s)
500
–500
0
–1ns
–0.5ns
0ns
0.5ns
1ns
E
Y
E
DI
AG
RAM
V
O
L
T
AG
E
(
V
)
EYE: ALL BITS
ULS: 10000/15600
Figure 61. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
05
72
7-04
4
200
–200
0
–1ns
–0.5ns
0ns
0.5ns
1ns
E
Y
E
D
IAG
RAM
V
O
L
T
AG
E
(
V
)
EYE: ALL BITS
ULS: 9600/15600
100
50
0
–150ps –100ps
–50ps
0ps
50ps
100ps
150ps
T
IE
J
IT
T
ER
HI
S
T
O
G
R
AM
(
H
it
s)
Figure 62. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
100
50
0
–150ps –100ps
–50ps
0ps
50ps
100ps
150ps
T
IE
JI
T
E
R
HI
S
T
O
G
RAM
(
H
it
s)
05
72
7-
04
2
200
400
–200
–400
0
–1ns
–0.5ns
0ns
0.5ns
1ns
E
Y
E
DI
AG
RA
M
V
O
L
T
AG
E
(
V
)
EYE: ALL BITS
ULS: 9599/15599
Figure 63. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Internal
Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4,
External 100 Ω Far Termination Only
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the
Memory Map section.
Table 8. Digital Output Coding
Code
(VIN + x) (VIN x),
Input Span = 2 V p-p (V)
Digital Output Offset Binary
(D11 ... D0)
4095
+1.00
1111 1111 1111
2048
0.00
1000 0000 0000
2047
0.000488
0111 1111 1111
0
1.00
0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 780 Mbps
(12 bits × 65 MSPS = 780 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up via the SPI to allow
encode rates as low as 5 MSPS. See the Memory Map section for
details on enabling this feature.
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